Hi, my friends and I are doing a project for an exam. We are trying to make a 4-bit up and down counter with the options to stop the counting,or load a number and then start the count. the problem occurs when we do the post-route simulation; the output changes when the clock is at 0, and there are multiple hazards that last for about 25-30 ps. Can someone help me? what are we doing wrong? here's the code. use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; entity esame2 is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; start_stop : in STD_LOGIC; up_down : in STD_LOGIC; value : in STD_LOGIC_VECTOR (3 downto 0); insert : in STD_LOGIC; num : out STD_LOGIC_VECTOR (3 downto 0)); end esame2; architecture RTL of esame2 is signal vet : STD_LOGIC_VECTOR (3 downto 0); begin process(reset, clock) begin if reset = '1' then vet <= "0000"; elsif (clock'event and clock = '1') then if(start_stop = '0' and reset = '0') then vet <= vet; elsif(insert = '1' and start_stop = '1' and reset = '0') then vet <= value; elsif(insert = '0' and reset = '0' and start_stop='1' and up_down ='1')then if(vet = "1111") then vet <= "0000"; else vet <= vet + 1; end if; elsif(up_down = '0')then if(vet = "0000") then vet <= "1111"; else vet <= vet - 1; end if; end if; end if; end process; num <= vet; end RTL;
I guess you should better not perform calculations with standard logic vectors. Use unsigned for it. You can also use the code brackets to format the code properly.
Paolo wrote: > and there are multiple hazards that last for about 25-30 ps. Thats normal. For example a overflow transition from 1111 to 0000 or vice versa like your underflow 0000 to 1111 causes all 4 bits to flip over. And they won't do it at the very same ps. And that are no hazarzd, just simple glitches. Those happen in every synchronous design with every clock cycle all over the world... > the problem occurs when we do the post-route simulation; You got it! > Can someone help me? what are we doing wrong? Do NEVER perform a post synthesis simulation. You will NOT need it. It does not give you more useful information than a behavioural (pre synthesize) simulation can do. A behavioural simulation is all you need for a synchronous design. At least I did not perform a post synthesize/translate/route/whatsoever simulation the last 15 years...
: Edited by Moderator