4-bit counter simulation problem

Hi, my friends and I are doing a project for an exam. We are trying to 
make a 4-bit up and down counter with the options to stop the 
counting,or load a number and then start the count. the problem occurs 
when we do the post-route simulation; the output changes when the clock 
is at 0, and there are multiple hazards that last for about 25-30 ps. 
Can someone help me? what are we doing wrong? here's the code.

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity esame2 is
    Port ( clock : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           start_stop : in  STD_LOGIC;
           up_down : in  STD_LOGIC;
           value : in  STD_LOGIC_VECTOR (3 downto 0);
           insert : in  STD_LOGIC;
           num : out  STD_LOGIC_VECTOR (3 downto 0));
end esame2;

architecture RTL of esame2 is
signal vet : STD_LOGIC_VECTOR (3 downto 0);
begin
process(reset, clock)
  begin
    if reset = '1' then
      vet <= "0000";
    elsif (clock'event and clock = '1') then
      if(start_stop = '0' and reset = '0') then
        vet <= vet;
  elsif(insert = '1' and start_stop = '1' and reset = '0') then
        vet <= value;
elsif(insert = '0' and reset = '0' and start_stop='1' and up_down 
='1')then
        if(vet = "1111") then
          vet <= "0000";
          else vet <= vet + 1;
        end if;
      elsif(up_down = '0')then
        if(vet = "0000") then
          vet <= "1111";
          else vet <= vet - 1;
        end if;
      end if;
    end if;
end process;
num <= vet;
end RTL;