I'am a beginner in veriglog development.
I don't understand why a part of my design is skipped when I synthesize
my design with Quartus 16.
in the RTL viewer I can see all my design, but in the map viewer a part
of my design is skipped.
I don't have an error or warning during the compilation.
I don't use the keyword of simulation like delay or fork.
What are the potential causes of this behavior of Quartus 16?
I think it can be because I don't load the data correctly into the
buffer of the skipped module.
thank in advance