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Hello everyone I'am a beginner in veriglog development. I don't understand why a part of my design is skipped when I synthesize my design with Quartus 16. in the RTL viewer I can see all my design, but in the map viewer a part of my design is skipped. I don't have an error or warning during the compilation. I don't use the keyword of simulation like delay or fork. What are the potential causes of this behavior of Quartus 16? I think it can be because I don't load the data correctly into the buffer of the skipped module. thank in advance
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All unsed logic is usualy optimized away. If you connect the output of your logic with pins from the chip, then you get the expected results. Duke
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Also check if your reset signal is correctly handled. If the logic optimizer detects that reset always will be active (since it is generated in a wrong way), it removes all affected parts of your design since they are useless.
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