EmbDev.net

Forum: FPGA, VHDL & Verilog Skipped part of design


Skipped part of design
von Op O. (Company: fgerg) (doomer5)

Rate this post
• ▲ useful
▼ not useful 
Hello everyone

I'am a beginner in veriglog development.
I don't understand why a part of my design is skipped when I synthesize 
my design with Quartus 16.
in the RTL viewer I can see all my design, but in the map viewer a part 
of my design is skipped.
I don't have an error or warning during the compilation.
I don't use the keyword of simulation like delay or fork.
What are the potential causes of this behavior of Quartus 16?
I think it can be because I don't load the data correctly into the 
buffer of the skipped module.

thank in advance

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: Skipped part of design
von Duke Scarring (Guest)

Rate this post
• ▲ useful
▼ not useful 
All unsed logic is usualy optimized away. If you connect the output of 
your logic with pins from the chip, then you get the expected results.

Duke

Report post Edit Delete Quote selected text Reply Reply with quote
Re: Skipped part of design
von Vancouver (Guest)

Rate this post
• ▲ useful
▼ not useful 
Also check if your reset signal is correctly handled. If the logic 
optimizer detects that reset always will be active (since it is 
generated in a wrong way), it removes all affected parts of your design 
since they are useless.

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.