Forum: FPGA, VHDL & Verilog Help in simulating ALU with register file

von Fadi C. (fadia)

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I need to design register file that is connected to an ALU in 
systemverilog, then simulate the top module to verify that operation are 
performed correctly.

I attached three modules, one for alu, register file, top module, and 
testbench for top module.


I am having trouble figuring out what to use for the output of the 
topalu module, since the output of the alu will be fed back to the write 
data port in register file. Once I figure this out I will figure out the 
issue with my test bench.


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