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Forum: FPGA, VHDL & Verilog if error on sequence detector


if error on sequence detector
von Rock B. (rocko445)

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Hello, i have the following error on every "if" and "case" line.
i am using quartus 2 'why i get these errors??

Thanks
*******************************************************
Error (10500): VHDL syntax error at case_vhdl.vhd(19) near text "clk"; 
expecting "(", or "'", or "."
Error (10500): VHDL syntax error at case_vhdl.vhd(19) near text "and"; 
expecting "(", or "'", or "."
Error (10500): VHDL syntax error at case_vhdl.vhd(32) near text "else"; 
expecting "end", or "(", or an identifier ("else" is a reserved 
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(40) near text "when"; 
expecting "end", or "(", or an identifier ("when" is a reserved 
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(47) near text "when"; 
expecting "end", or "(", or an identifier ("when" is a reserved 
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(56) near text "when"; 
expecting "end", or "(", or an identifier ("when" is a reserved 
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(63) near text "when"; 
expecting "end", or "(", or an identifier ("when" is a reserved 
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(65) near text "case"; 
expecting "if"
Error (10500): VHDL syntax error at case_vhdl.vhd(70) near text "begin"; 
expecting ":=", or "<="
Error (10500): VHDL syntax error at case_vhdl.vhd(76) near text 
"process";  expecting "if"
**********************************************************
1
library IEEE;

2
use IEEE.STD_LOGIC_1164.all;

3
entity seqdeta is

4
 port (clk:in STD_LOGIC;

5
       clr:in STD_LOGIC;

6
     din:in STD_LOGIC;

7
     dout:in STD_LOGIC);

8
end seqdeta;     

9
10
architecture seqdeta of seqdeta is

11
type state_type is (s0, s2, s3, s4);

12
signal present_state,next_state: state_type;

13
begin  

14
15
 sreg: process(clk,clr)

16
 begin

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        if clr='1' then 

18
             present_state<=s0;

19
        elseif clk'event and clk='1' then

20
                present_state<=next_state;      

21
         end if;

22
 end process;

23
 

24
 C1: process(present_state, din)

25
 begin

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   case present_state is

27
       when s0=>

28
        if din='1' then

29
        next_state<=s1;

30
       else

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         next_state<=s0;

32
      else if;

33
      when s1=>

34
        if din='1' then 

35
          next_state<=s2;

36
       else 

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         next_state<=s0;

38
          end if;      

39
         

40
      when s2=>

41
         if din='0' then

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            next_state<=s3;

43
        else

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           next_state<=s2;

45
           end if;

46
        

47
        when s3=>

48
         if din='1' then

49
            next_state<=s4;

50
        else

51
           next_state<=s0;

52
           end if;

53
        

54
        

55
        

56
        when s4=>

57
         if din='0' then

58
            next_state<=s0;

59
        else

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           next_state<=s2;

61
           end if;

62
        

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        when others =>

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          null;

65
      end case;

66
  

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     end process;  

68
    

69
C2: process(present_state)

70
begin

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   if present_state=s4 then

72
      dout<='1';

73
  else

74
      dout<='0';

75
  end if;

76
end process;

77
end seqdeta;


  


  



  

  
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    Re: if error on sequence detector
  


  

    

      von
      
        Markus F.
        (mfro)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Look very closely what you have written and where the first error 
message appears, it's pretty easy to spot. Hint: you're missing a 
termination at one of your if clauses...

  


  




  

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    Re: if error on sequence detector
  


  

    

      von
      
        Rock B.
        (rocko445)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Hello , my first error is in the following "if" shown bellow

i used , end if , i ended every statement inside it with ";"
where did i go wrong?


**************************************************
if clr='1' then
             present_state<=s0;
        elseif clk'event and clk='1' then
                present_state<=next_state;
end if;
****************************************************

Thanks

  


  




  

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    Re: if error on sequence detector
  


  

    

      von
      
        Markus F.
        (mfro)
        
      
      


      
    


    

      
    

    

    

  
  


  

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check the same for your first case label.

  


  




  

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    Re: if error on sequence detector
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Rock B. wrote:
> where did i go wrong?
Pls read and follow the instructions for the edit box. Here a shot 
summary:
1
Reply

2
Rules — please read before posting

3
    Post long source code as attachment, not in the text

4
Formatting options

5
    [vhdl]VHDL code[/vhdl]


  


  



  

  
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