EmbDev.net

Forum: FPGA, VHDL & Verilog if error on sequence detector


Author: Rock Bog (rocko445)
Posted on:

Rate this post
0 useful
not useful
Hello, i have the following error on every "if" and "case" line.
i am using quartus 2 'why i get these errors??

Thanks
*******************************************************
Error (10500): VHDL syntax error at case_vhdl.vhd(19) near text "clk"; 
expecting "(", or "'", or "."
Error (10500): VHDL syntax error at case_vhdl.vhd(19) near text "and"; 
expecting "(", or "'", or "."
Error (10500): VHDL syntax error at case_vhdl.vhd(32) near text "else"; 
expecting "end", or "(", or an identifier ("else" is a reserved 
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(40) near text "when"; 
expecting "end", or "(", or an identifier ("when" is a reserved 
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(47) near text "when"; 
expecting "end", or "(", or an identifier ("when" is a reserved 
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(56) near text "when"; 
expecting "end", or "(", or an identifier ("when" is a reserved 
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(63) near text "when"; 
expecting "end", or "(", or an identifier ("when" is a reserved 
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(65) near text "case"; 
expecting "if"
Error (10500): VHDL syntax error at case_vhdl.vhd(70) near text "begin"; 
expecting ":=", or "<="
Error (10500): VHDL syntax error at case_vhdl.vhd(76) near text 
"process";  expecting "if"
**********************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity seqdeta is
 port (clk:in STD_LOGIC;
       clr:in STD_LOGIC;
     din:in STD_LOGIC;
     dout:in STD_LOGIC);
end seqdeta;     

architecture seqdeta of seqdeta is
type state_type is (s0, s2, s3, s4);
signal present_state,next_state: state_type;
begin  

 sreg: process(clk,clr)
 begin
        if clr='1' then 
             present_state<=s0;
        elseif clk'event and clk='1' then
                present_state<=next_state;      
         end if;
 end process;
 
 C1: process(present_state, din)
 begin
   case present_state is
       when s0=>
        if din='1' then
        next_state<=s1;
       else
         next_state<=s0;
      else if;
      when s1=>
        if din='1' then 
          next_state<=s2;
       else 
         next_state<=s0;
          end if;      
         
      when s2=>
         if din='0' then
            next_state<=s3;
        else
           next_state<=s2;
           end if;
        
        when s3=>
         if din='1' then
            next_state<=s4;
        else
           next_state<=s0;
           end if;
        
        
        
        when s4=>
         if din='0' then
            next_state<=s0;
        else
           next_state<=s2;
           end if;
        
        when others =>
          null;
      end case;
  
     end process;  
    
C2: process(present_state)
begin
   if present_state=s4 then
      dout<='1';
  else
      dout<='0';
  end if;
end process;
end seqdeta;

: Edited by Moderator
Author: Markus F. (mfro)
Posted on:

Rate this post
0 useful
not useful
Look very closely what you have written and where the first error 
message appears, it's pretty easy to spot. Hint: you're missing a 
termination at one of your if clauses...

Author: Rock Bog (rocko445)
Posted on:

Rate this post
0 useful
not useful
Hello , my first error is in the following "if" shown bellow

i used , end if , i ended every statement inside it with ";"
where did i go wrong?


**************************************************
if clr='1' then
             present_state<=s0;
        elseif clk'event and clk='1' then
                present_state<=next_state;
end if;
****************************************************

Thanks

Author: Markus F. (mfro)
Posted on:

Rate this post
0 useful
not useful
check the same for your first case label.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Rock B. wrote:
> where did i go wrong?
Pls read and follow the instructions for the edit box. Here a shot 
summary:
Reply
Rules — please read before posting
    Post long source code as attachment, not in the text
Formatting options
    [vhdl]VHDL code[/vhdl]

: Edited by Moderator

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig