Hello, i have the following error on every "if" and "case" line.
i am using quartus 2 'why i get these errors??
Thanks
*******************************************************
Error (10500): VHDL syntax error at case_vhdl.vhd(19) near text "clk";
expecting "(", or "'", or "."
Error (10500): VHDL syntax error at case_vhdl.vhd(19) near text "and";
expecting "(", or "'", or "."
Error (10500): VHDL syntax error at case_vhdl.vhd(32) near text "else";
expecting "end", or "(", or an identifier ("else" is a reserved
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(40) near text "when";
expecting "end", or "(", or an identifier ("when" is a reserved
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(47) near text "when";
expecting "end", or "(", or an identifier ("when" is a reserved
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(56) near text "when";
expecting "end", or "(", or an identifier ("when" is a reserved
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(63) near text "when";
expecting "end", or "(", or an identifier ("when" is a reserved
keyword), or a sequential statement
Error (10500): VHDL syntax error at case_vhdl.vhd(65) near text "case";
expecting "if"
Error (10500): VHDL syntax error at case_vhdl.vhd(70) near text "begin";
expecting ":=", or "<="
Error (10500): VHDL syntax error at case_vhdl.vhd(76) near text
"process"; expecting "if"
**********************************************************1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.all;
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3 | entity seqdeta is
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4 | port (clk:in STD_LOGIC;
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5 | clr:in STD_LOGIC;
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6 | din:in STD_LOGIC;
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7 | dout:in STD_LOGIC);
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8 | end seqdeta;
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9 |
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10 | architecture seqdeta of seqdeta is
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11 | type state_type is (s0, s2, s3, s4);
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12 | signal present_state,next_state: state_type;
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13 | begin
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14 |
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15 | sreg: process(clk,clr)
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16 | begin
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17 | if clr='1' then
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18 | present_state<=s0;
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19 | elseif clk'event and clk='1' then
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20 | present_state<=next_state;
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21 | end if;
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22 | end process;
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23 |
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24 | C1: process(present_state, din)
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25 | begin
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26 | case present_state is
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27 | when s0=>
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28 | if din='1' then
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29 | next_state<=s1;
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30 | else
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31 | next_state<=s0;
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32 | else if;
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33 | when s1=>
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34 | if din='1' then
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35 | next_state<=s2;
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36 | else
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37 | next_state<=s0;
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38 | end if;
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39 |
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40 | when s2=>
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41 | if din='0' then
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42 | next_state<=s3;
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43 | else
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44 | next_state<=s2;
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45 | end if;
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46 |
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47 | when s3=>
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48 | if din='1' then
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49 | next_state<=s4;
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50 | else
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51 | next_state<=s0;
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52 | end if;
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53 |
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54 |
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55 |
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56 | when s4=>
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57 | if din='0' then
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58 | next_state<=s0;
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59 | else
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60 | next_state<=s2;
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61 | end if;
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62 |
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63 | when others =>
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64 | null;
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65 | end case;
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66 |
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67 | end process;
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68 |
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69 | C2: process(present_state)
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70 | begin
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71 | if present_state=s4 then
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72 | dout<='1';
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73 | else
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74 | dout<='0';
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75 | end if;
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76 | end process;
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77 | end seqdeta;
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