Forum: FPGA, VHDL & Verilog how to scale output of butterfly unit radix 2 for further stages

Author: Pravesh Rathee (Company: MTech) (rathee)
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I am designing 8 point FFT by radix 2 using verilog. m using radix 2 
butterfly unit with 8 bits input and so output i expect to be 8 bit so 
that i can use this structure again and again for further sta. i am 
applying DIT. if i consider my twiddle factors are of 8 bits stored 
somewhere then i multiply to one of butterfly inputs result is 16 
bits,and when added/subtracted to other input output is for sure going 
to be min 16 bit/ 17 bit. but i expect my output to be of 8 bit so that 
same butterfly with 8 bit input can be used. how do i scale this without 
loss of accuracy.
please reply if you exactly dont understand my problem.

Author: Duke Scarring (Guest)
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Pravesh R. wrote:
> how do i scale this without loss of accuracy.
I would design the filter with a higher level language like python or 
There it's more easy to see which internal bitwidth are required to 
avoid overflows.


Author: ruchi chouhan (Guest)
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Obviously if you multiply two 8-bit numbers and then want the result to 
fit in 8 bits you will loose some precision.

You need to make a decision regarding how much error you are willing to 
accumulate in each stage. If you are not willing to have any error then 
you will need to increase the number of bits in each stage.

When doing fixed point arithmetic like this its often useful to 
interpret the vectors as scaled integers. For signed numbers you could 
use the following scale...

1000_0000... = -1.00...
0000_0000... = 0.00...
0111_1111... = 0.99...

The multiplication of two N-bit signed vectors results in a vector that 
is 2*N - 1 bits long. When using scaled integers you would then just 
take the upper N bits of the result to get back to your original scale.


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