i find my self back into vhdl, after 2-3 years. i feel quite rusty and
in need of a push. i want to test a uart link on hardware(ProAsic3).
Have been using the coreIP from Actel with no problems, but need
something faster, and came across the code in
http://www.lothar-miller.de/s9y/categories/42-RS232. I am attaching two
simulations using that uart. preSynth and postSynth.
My tb, reads a hex number from a file (60 bits = 6 bytes with start/stop
bits), and then shifts the bits onto the RX line of the uart. System
clock is 100MHz and tested on both 9600 and 115200 baud rates with same
PreSynth simulation is fine. Correct reception and packing of bytes onto
PostSynth simulation...need a push. cant see my error. loads of Xx..
Note that the PostSynth simulation is very zoomed (see the RESETn
ps. i run the tool chain all the way, achieving a final speed of
>100MHz, which is promising