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Forum: FPGA, VHDL & Verilog RS232 from http://www.lothar-miller.de.


Author: SparkyT (Guest)
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hi all
i find my self back into vhdl, after 2-3 years. i feel quite rusty and 
in need of a push. i want to test a uart link on hardware(ProAsic3). 
Have been using the coreIP from Actel with no problems, but need 
something faster, and came across the code in
http://www.lothar-miller.de/s9y/categories/42-RS232. I am attaching two 
simulations using that uart. preSynth and postSynth.
My tb, reads a hex number from a file (60 bits = 6 bytes with start/stop 
bits), and then shifts the bits onto the RX line of the uart. System 
clock is 100MHz and tested on both 9600 and 115200 baud rates with same 
results.
PreSynth simulation is fine. Correct reception and packing of bytes onto 
a frame.
PostSynth simulation...need a push. cant see my error. loads of Xx..
Note that the PostSynth  simulation is very zoomed (see the RESETn 
initial toggle)

ps. i run the tool chain all the way, achieving a final speed of 
>100MHz, which is promising

Thanks

Author: SparkyT (Guest)
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Hi again.
Fixed it. Initialization values.
I use Libero....
T

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