Hello , the smallest component is a halfadder, but its not implemented
in the example bellow,
where do i add the code of the half adder
1  sum <= a xor b ;

2  carry <= a and b ;

Thanks
1  top module(full adder) entity declaration

2  entity fulladder is

3  port (a : in std_logic;

4  b : in std_logic;

5  cin : in std_logic;

6  sum : out std_logic;

7  carry : out std_logic

8  );

9  end fulladder;

10  top module architecture declaration.

11  architecture behavior of fulladder is

12  submodule(half adder) is declared as a component before the keyword "begin".

13  component halfadder

14  port(

15  a : in std_logic;

16  b : in std_logic;

17  sum : out std_logic;

18  carry : out std_logic

19  );

20  end component;

21  All the signals are declared here,which are not a part of the top module.

22  These are temporary signals like 'wire' in Verilog.

23  signal s1,c1,c2 : std_logic:='0';

24  
25  begin

26  instantiate and do port map for the first half adder.

27  HA1 : halfadder port map (

28  a => a,

29  b => b,

30  sum => s1,

31  carry => c1

32  );

33  instantiate and do port map for the second half adder.

34  HA2 : halfadder port map (

35  a => s1,

36  b => cin,

37  sum => sum,

38  carry => c2

39  );

40  carry <= c1 or c2; final carry calculation

41  
42  end;
