EmbDev.net

Forum: FPGA, VHDL & Verilog portmap problem, implementing the smallest part


portmap problem, implementing the smallest part
von Rock B. (rocko445)

Rate this post
• ▲ useful
▼ not useful 
Hello , the smallest component is a halfadder, but its not implemented 
in the example  bellow,
where do i add the code of the half adder
1
sum <= a xor b ;

2
carry <= a and b ;


Thanks

1
--top module(full adder) entity declaration

2
entity fulladder is

3
    port (a : in std_logic;

4
            b : in std_logic;

5
           cin : in std_logic;

6
           sum : out std_logic;

7
           carry : out std_logic

8
         );

9
end fulladder;

10
--top module architecture declaration.

11
architecture behavior of fulladder is

12
--sub-module(half adder) is declared as a component before the keyword "begin".

13
   component halfadder

14
    port(

15
         a : in std_logic;

16
         b : in std_logic;

17
         sum : out std_logic;

18
         carry : out std_logic

19
        );

20
    end component;

21
--All the signals are declared here,which are not a part of the top module.

22
--These are temporary signals like 'wire' in Verilog.

23
signal s1,c1,c2 : std_logic:='0';

24
25
begin

26
--instantiate and do port map for the first half adder.

27
  HA1 : halfadder port map (

28
          a => a,

29
          b => b,

30
          sum => s1,

31
          carry => c1

32
        );

33
--instantiate and do port map for the second half adder.

34
 HA2 : halfadder port map (

35
          a => s1,

36
          b => cin,

37
         sum => sum,

38
         carry => c2

39
        );

40
carry <= c1 or c2;  --final carry calculation

41
42
end;


  


  



  

  
:
    Edited by Moderator
  

  


  

    Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
  







      

      



  

    Re: portmap problem, implementing the smallest part
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

  Rate this post
  

  •
  
  ▲ useful 
  

  ▼ not useful 
  		
  

  


  

      
Rock B. wrote:
> where do i add the code of the half adder
You add it in an entity named like the declared and instantiated 
component "halfadder". Someway like this:
1
entity halfadder is

2
  port(

3
    a : in std_logic;

4
    b : in std_logic;

5
    sum : out std_logic;

6
    carry : out std_logic

7
  );

8
end halfadder;

9
:

10
:

11
:

A little hint: the web is full of code doing exactly that.
That Google thing helps you finding it:
https://www.google.com/search?q=vhdl+half+adder+full+adder


BTW: pls read and follow the instructions a few line above every edit 
box and use the [vhdl] tags instead that lines of sparkling stars!

  


  



  

  
:
    Edited by Moderator
  

  


  

    Report post Edit Delete Quote selected text Reply Reply with quote
  








    

    

       Watch this topic

      |
         Disable multi-page view

    

        


Please log in before posting. Registration is free and takes only a minute.



  Existing account

  


  
  

  
    

      

        
          
        
        
          
        
      

      

        
          
        
        
          
        
      

    


    
    
    





  Do you have a Google/GoogleMail account? No registration required!

  Log in with Google account
  





  No account? Register here.