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Forum: FPGA, VHDL & Verilog portmap problem, implementing the smallest part


von Rock B. (rocko445)


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Hello , the smallest component is a halfadder, but its not implemented 
in the example  bellow,
where do i add the code of the half adder
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sum <= a xor b ;
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carry <= a and b ;

Thanks
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--top module(full adder) entity declaration
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entity fulladder is
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    port (a : in std_logic;
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            b : in std_logic;
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           cin : in std_logic;
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           sum : out std_logic;
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           carry : out std_logic
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         );
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end fulladder;
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--top module architecture declaration.
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architecture behavior of fulladder is
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--sub-module(half adder) is declared as a component before the keyword "begin".
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   component halfadder
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    port(
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         a : in std_logic;
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         b : in std_logic;
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         sum : out std_logic;
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         carry : out std_logic
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        );
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    end component;
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--All the signals are declared here,which are not a part of the top module.
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--These are temporary signals like 'wire' in Verilog.
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signal s1,c1,c2 : std_logic:='0';
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begin
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--instantiate and do port map for the first half adder.
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  HA1 : halfadder port map (
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          a => a,
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          b => b,
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          sum => s1,
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          carry => c1
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        );
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--instantiate and do port map for the second half adder.
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 HA2 : halfadder port map (
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          a => s1,
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          b => cin,
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         sum => sum,
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         carry => c2
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        );
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carry <= c1 or c2;  --final carry calculation
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end;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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Rock B. wrote:
> where do i add the code of the half adder
You add it in an entity named like the declared and instantiated 
component "halfadder". Someway like this:
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entity halfadder is
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  port(
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    a : in std_logic;
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    b : in std_logic;
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    sum : out std_logic;
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    carry : out std_logic
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  );
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end halfadder;
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:
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:
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:
A little hint: the web is full of code doing exactly that.
That Google thing helps you finding it:
https://www.google.com/search?q=vhdl+half+adder+full+adder


BTW: pls read and follow the instructions a few line above every edit 
box and use the [vhdl] tags instead that lines of sparkling stars!

: Edited by Moderator

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