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Forum: FPGA, VHDL & Verilog portmap problem, implementing the smallest part


Author: Rock Bog (rocko445)
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Hello , the smallest component is a halfadder, but its not implemented 
in the example  bellow,
where do i add the code of the half adder
sum <= a xor b ;
carry <= a and b ;

Thanks
--top module(full adder) entity declaration
entity fulladder is
    port (a : in std_logic;
            b : in std_logic;
           cin : in std_logic;
           sum : out std_logic;
           carry : out std_logic
         );
end fulladder;
--top module architecture declaration.
architecture behavior of fulladder is
--sub-module(half adder) is declared as a component before the keyword "begin".
   component halfadder
    port(
         a : in std_logic;
         b : in std_logic;
         sum : out std_logic;
         carry : out std_logic
        );
    end component;
--All the signals are declared here,which are not a part of the top module.
--These are temporary signals like 'wire' in Verilog.
signal s1,c1,c2 : std_logic:='0';

begin
--instantiate and do port map for the first half adder.
  HA1 : halfadder port map (
          a => a,
          b => b,
          sum => s1,
          carry => c1
        );
--instantiate and do port map for the second half adder.
 HA2 : halfadder port map (
          a => s1,
          b => cin,
         sum => sum,
         carry => c2
        );
carry <= c1 or c2;  --final carry calculation

end;

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

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Rock B. wrote:
> where do i add the code of the half adder
You add it in an entity named like the declared and instantiated 
component "halfadder". Someway like this:
entity halfadder is
  port(
    a : in std_logic;
    b : in std_logic;
    sum : out std_logic;
    carry : out std_logic
  );
end halfadder;
:
:
:
A little hint: the web is full of code doing exactly that.
That Google thing helps you finding it:
https://www.google.com/search?q=vhdl+half+adder+full+adder


BTW: pls read and follow the instructions a few line above every edit 
box and use the [vhdl] tags instead that lines of sparkling stars!

: Edited by Moderator

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