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Forum: FPGA, VHDL & Verilog Hardware Target shutdown problem in nexys 4 ddr


Author: Lakshita J. (lakshita)
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Hello,

I am working on Nexys 4 ddr FPGA board.I have done 
synthesis,implementation and bitsream generation succesfully but when I 
programmed the bit file into the fpga board,the output is showing 
results for n=5,20,60,80,100 bits and  above 100 bits the hardware 
server automatically gets disconnect and the below error occurs.


ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: 
localhost:3121/xilinx_tcf/Digilent/210292743548A

please provide any solution to how to fix the above problem

Author: Hämorrhoiden haben auch Gefühle (Guest)
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Lakshita J. wrote:
> n=5,20,60,80,100 bits and  above 100 bits

What is n?

Please provide full source code.

Author: Hämorrhoiden haben auch Gefühle (Guest)
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And please report the 7 errors and 266 warnings. This must be utterly 
wrong so the Hardwaremanager fault might just be a symptom of many other 
errors.

Author: Lakshita J. (lakshita)
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> And please report the 7 errors and 266 warnings. This must be
> utterly
> wrong so the Hardwaremanager fault might just be a symptom of many other
> errors.


There are no such errors and warnings after implementation ,it may be 
due to previous files I have implemented design again and the problem i 
am facing is of hardware server gets shutdown.The screenshot of my 
problem is attached and also I have attached verilog code

Author: Hobbyfleischer (Guest)
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Well, there is no constraints file where the FPGA IOs are mapped to the 
signal names. Please provide the complete project. Without constraints 
there is no way to build the bitstream.

Author: Lakshita J. (lakshita)
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> Well, there is no constraints file where the FPGA IOs are mapped
> to the
> signal names. Please provide the complete project. Without constraints
> there is no way to build the bitstream.


I have attached the xdc file of nexys 4 ddr. In constraint file,I have 
uncommented only this line

set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports 
{ clk }];

because I am using virtual input output(VIOs) for generating bit file.

Author: Lakshita J. (lakshita)
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After Implementation I am getting this warning, what does it mean?

[Power 33-332] Found switching activity that implies high-fanout reset 
nets being asserted for excessive periods of time which may result in 
inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints 
Advisor in the GUI from Tools > Power Constraints Advisor or run 
report_power with the -advisory option to generate a text report.

It may be possible because of this hardware server gets shutdown 
automatically and not displaying any output.

For smaller number of bits,this warning is not there that's why it is 
working

If anybody knows how to fix this problem then please provide any 
suggestions

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