Forum: FPGA, VHDL & Verilog Fullbuffer for local image operations

von Tom S. (torntom)

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I want to design a "fullbuffer" to better handle image operators like 
sobel on a fpga. It is designed to be generic, so that the mask height, 
mask width (used to define the pixels the local operator is executed 
on), the pixel data width and the width of the image (in this case 
mask_width + linebuffer_length = image width) can be tuned. I have 
attached an image to better demonstrate the functionality (The example 
uses a 3x3 mask and therefore 2 linebuffers to cache needed pixels). If 
necessary I can describe the functionality in more detail. Unfortunately 
there is a bus conflict while writing the "mask_ffs" signal (a 2d array 
that is forming the flipflops of the mask) in the for generate loop, 
which is instantiating the linebuffers (specificly in the line that 
says: "dout => mask_ffs(i+1, 0)" ). I could not detect any mistakes in 
my indices, or my coding.
I would be very thankful if you could help me figure out the mistake.
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;

use work.utils.all;    
-- defines constants for generics and type "generic_port_matrix" a 2d array(mask_height-1 downto 0, mask_width-1 downto 0) of std_logic_vector(data_width-1 downto 0) (first the y coord and then the x coord, with 0, 0 in the bottom right corner if you are using the attached image as reference)

entity fullbuffer is
        generic (
                linebuffer_length : integer := linebuffer_length;
                data_width : integer := data_width;
                mask_width : integer := mask_width;
                mask_height : integer := mask_height
        port (
                clk : in std_logic;
                we : in std_logic;
                din : in std_logic_vector(data_width-1 downto 0);
                dout : out generic_port_matrix
end fullbuffer;

architecture fullbuffer_arch of fullbuffer is

        signal mask_ffs : generic_port_matrix;

        type generic_vector is array(mask_height-1 downto 0) of std_logic_vector(data_width-1 downto 0);
        signal mask_out : generic_vector;


        -- output mask
        dout <= mask_ffs;

        -- instantiate the linebuffers
        for i in 0 to mask_height-2 generate

                linebuffer: entity work.linebuffer
                generic map (
                        length => linebuffer_length,
                        data_width => data_width
                port map (
                        clk => clk,              -- in
                        we => we,                -- in
                        din => mask_out(i),      -- in
                        dout => mask_ffs(i+1, 0) -- out

        end generate line_generate;

        process (clk)
                if (clk'event and clk = '1') then
                        if (we = '1') then

                                -- shift registers of mask
                                for i in 0 to mask_height-1 loop
                                        for j in 0 to mask_width-2 loop
                                                mask_ffs(i, j+1) <= mask_ffs(i, j);
                                        end loop;

                                        mask_out(i) <= mask_ffs(i, mask_width-1);
                                end loop;

                                -- input new pixel from sensor
                                mask_ffs(0, 0) <= din;
                        end if;
                end if;
        end process;

end fullbuffer_arch;


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