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Forum: FPGA, VHDL & Verilog Vhdl project: mini-router


von Lucy (Guest)


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I have a project about a mini router, I wrote the source code and the 
testbech and it seems to work, but I'm not sure everything is correct 
because I'm new in vhdl codes. Could someone please check it? I ll share 
my codes and the test of the project.

von Dr. Emmett L. Brown (Guest)


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For debug/verifying purposes, it woulde be fine to have an additional 
output whichs tells the sourceport (Link1 or link2) of the routed data.

von Luciana (luciana)


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Dr. Emmett L. Brown wrote:
> For debug/verifying purposes, it woulde be fine to have an additional
> output whichs tells the sourceport (Link1 or link2) of the routed data.

1:So you think my work is ok, right? You are just suggesting me how to 
improve it?
2: Should I add the 2 output ports to the entity of the mini router?

von Dr. Emmett L. Brown (Guest)


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Luciana wrote:
> Dr. Emmett L. Brown wrote:
>> For debug/verifying purposes, it woulde be fine to have an additional
>> output whichs tells the sourceport (Link1 or link2) of the routed data.
>
> 1:So you think my work is ok, right? You are just suggesting me how to
> improve it?

No, not to improve it, just to make it test-able.
See Design for test: https://en.wikipedia.org/wiki/Design_for_testing

Test coverage is also important, and have a look to UVVM: 
https://emlogic.no/uvvm/

von vancouver (Guest)


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use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

Never use both of them. Numeric is suffcient.

Besides that, I don't see any problems (assuming to simulation results 
are correct). But get used to write source code comments in english, so 
everybody can understand them :-)

von Luciana (luciana)


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thank you very much

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