Vhdl project: mini-router

Guest #7267870 
I have a project about a mini router, I wrote the source code and the 
testbech and it seems to work, but I'm not sure everything is correct 
because I'm new in vhdl codes. Could someone please check it? I ll share 
my codes and the test of the project.
Attached files:
Reply Quote Edit Move Thread sperren Slow mode Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report Thanks
Guest 
For debug/verifying purposes, it woulde be fine to have an additional 
output whichs tells the sourceport (Link1 or link2) of the routed data.
Reply Quote Edit Delete Report Thanks 
Dr. Emmett L. Brown wrote:
> For debug/verifying purposes, it woulde be fine to have an additional
> output whichs tells the sourceport (Link1 or link2) of the routed data.

1:So you think my work is ok, right? You are just suggesting me how to 
improve it?
2: Should I add the 2 output ports to the entity of the mini router?
Reply Quote Edit Delete Report Thanks
Guest 
Luciana wrote:
> Dr. Emmett L. Brown wrote:
>> For debug/verifying purposes, it woulde be fine to have an additional
>> output whichs tells the sourceport (Link1 or link2) of the routed data.
>
> 1:So you think my work is ok, right? You are just suggesting me how to
> improve it?

No, not to improve it, just to make it test-able.
See Design for test: https://en.wikipedia.org/wiki/Design_for_testing

Test coverage is also important, and have a look to UVVM: 
https://emlogic.no/uvvm/
Reply Quote Edit Delete Report Thanks
Guest 
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

Never use both of them. Numeric is suffcient.

Besides that, I don't see any problems (assuming to simulation results 
are correct). But get used to write source code comments in english, so 
everybody can understand them :-)
Reply Quote Edit Delete Report Thanks
(Company: word wipe)

Dr. Emmett L. Brown wrote:

Luciana wrote:

Dr. Emmett L. Brown wrote:

For debug/verifying purposes, it woulde be fine to have an additional output whichs tells the sourceport (Link1 or link2) of the routed data.

1:So you think my work is ok, right? You are just suggesting me how to improve it?

No, not to improve it, just to make it test-able. See Design for test: https://en.wikipedia.org/wiki/Design_for_testing https://drivemad.io/home

Test coverage is also important, and have a look to UVVM: https://emlogic.no/uvvm/

I agree with you, it is best to choose one or the other and never combine them. The use of numbers is adequate.

Reply Quote Edit Delete Report Thanks

I recommend asking for feedback on forums dedicated to VHDL or digital design. There, experienced users can review your code and testbench to ensure everything is correct. If you need help accessing your Airtel router settings for any reason, you can refer to this guide at https://routerctrl.com/airtel-router-login/. It provides step-by-step instructions on how to log in and make changes to your router settings. Good luck with your project!

Reply Quote Edit Delete Report Thanks
Watch this topic

Reply

A question of your own? This thread is over 3 years old. Ask it in a thread of its own – more people read along there, and it gets answered more often and sooner.

Start a new thread

A fix, an addition or feedback on this thread? Then reply here.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.