I have a project about a mini router, I wrote the source code and the testbech and it seems to work, but I'm not sure everything is correct because I'm new in vhdl codes. Could someone please check it? I ll share my codes and the test of the project.
Attached files:
-
1.png
170 KB
For debug/verifying purposes, it woulde be fine to have an additional output whichs tells the sourceport (Link1 or link2) of the routed data.
Dr. Emmett L. Brown wrote: > For debug/verifying purposes, it woulde be fine to have an additional > output whichs tells the sourceport (Link1 or link2) of the routed data. 1:So you think my work is ok, right? You are just suggesting me how to improve it? 2: Should I add the 2 output ports to the entity of the mini router?
Luciana wrote: > Dr. Emmett L. Brown wrote: >> For debug/verifying purposes, it woulde be fine to have an additional >> output whichs tells the sourceport (Link1 or link2) of the routed data. > > 1:So you think my work is ok, right? You are just suggesting me how to > improve it? No, not to improve it, just to make it test-able. See Design for test: https://en.wikipedia.org/wiki/Design_for_testing Test coverage is also important, and have a look to UVVM: https://emlogic.no/uvvm/
use IEEE.std_logic_unsigned.all; use IEEE.numeric_std.all; Never use both of them. Numeric is suffcient. Besides that, I don't see any problems (assuming to simulation results are correct). But get used to write source code comments in english, so everybody can understand them :-)
Watch this topic
Disable multi-page viewPlease log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.