I have a project about a mini router, I wrote the source code and the testbech and it seems to work, but I'm not sure everything is correct because I'm new in vhdl codes. Could someone please check it? I ll share my codes and the test of the project.
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For debug/verifying purposes, it woulde be fine to have an additional output whichs tells the sourceport (Link1 or link2) of the routed data.
Dr. Emmett L. Brown wrote: > For debug/verifying purposes, it woulde be fine to have an additional > output whichs tells the sourceport (Link1 or link2) of the routed data. 1:So you think my work is ok, right? You are just suggesting me how to improve it? 2: Should I add the 2 output ports to the entity of the mini router?
Luciana wrote: > Dr. Emmett L. Brown wrote: >> For debug/verifying purposes, it woulde be fine to have an additional >> output whichs tells the sourceport (Link1 or link2) of the routed data. > > 1:So you think my work is ok, right? You are just suggesting me how to > improve it? No, not to improve it, just to make it test-able. See Design for test: https://en.wikipedia.org/wiki/Design_for_testing Test coverage is also important, and have a look to UVVM: https://emlogic.no/uvvm/
use IEEE.std_logic_unsigned.all; use IEEE.numeric_std.all; Never use both of them. Numeric is suffcient. Besides that, I don't see any problems (assuming to simulation results are correct). But get used to write source code comments in english, so everybody can understand them :-)
Dr. Emmett L. Brown wrote: > Luciana wrote: >> Dr. Emmett L. Brown wrote: >>> For debug/verifying purposes, it woulde be fine to have an additional >>> output whichs tells the sourceport (Link1 or link2) of the routed data. >> >> 1:So you think my work is ok, right? You are just suggesting me how to >> improve it? > > No, not to improve it, just to make it test-able. > See Design for test: https://en.wikipedia.org/wiki/Design_for_testing https://drivemad.io/home > > Test coverage is also important, and have a look to UVVM: > https://emlogic.no/uvvm/ I agree with you, it is best to choose one or the other and never combine them. The use of numbers is adequate.
It's great that you've completed your mini-router project in VHDL. If you're new to VHDL, it's understandable to have some doubts about your code.
I recommend asking for feedback on forums dedicated to VHDL or digital design. There, experienced users can review your code and testbench to ensure everything is correct. If you need help accessing your Airtel router settings for any reason, you can refer to this guide at https://routerctrl.com/airtel-router-login/. It provides step-by-step instructions on how to log in and make changes to your router settings. Good luck with your project!
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