# Forum: FPGA, VHDL & Verilog Verilog autodetect signal

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Hi, I've been wrestling with this for a bit and was hoping for some
pointers :-)

Consider a module that has as input signal A, a clock, and outputs X and
Y.

Let signal 1 be a repeating signal of 6 short high pulses (4 clock
cycles per pulse), followed by a longer period (50 clock cycles) of low
signal.

Let signal 2 be a repeating signal of 10 short high pulses (3 clock
cycles per pulse), followed by a longer period (48 clock cycles) of low
signal.

I'm not looking for code because I feel there is something to learn
here, but assume I'd like the following:

If signal 1 is present on input A --> X is always high and Y is always
0.
If signal 2 is present on input A --> Y is always high and X is always
0.

Could someone point me a bit in which direction I should be looking to
realise this on a hardware in Verilog?

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Joey O. wrote:
> If signal 1 is present on input A --> X is always high and Y is always 0.
> If signal 2 is present on input A --> Y is always high and X is always 0.
1. can you draw that in a timing diagram? What means "present"? Because
the signals are both always "present" as 0 or as 1.
2. you must set up a priority order for the result because you can not
get both of them.

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Thanks for replying so quickly!

Typing this from my phone so I might be able to provide a diagram at a
later time.

What I mean is that I have two possible external input signals on input
A. Signal 1 on a blue wire or signal 2 on a red wire. Either signal 1
enters input A, or signal 2. This depends on which wire the user
connects.

I want to write some code which detects whether signal 1 or signal 2 is
being input (which I can probably do with some pulse counts) and
according to that outcome I'd like to drive the outputs X and Y forever
high/low according to the way I specified.

Lets say "if signal 1 is fed into the device" led X is on and led Y is
off until reset or poweroff and vice versa for signal 2.

Sorry for the messy explanation. Hope this makes a bit more clear as to
what I'm trying to achieve.

: Edited by User

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Joey O. wrote:
Lets try it from the end:
> according to that outcome I'd like to drive the outputs X and Y forever
> high/low according to the way I specified.
So you only must drive X the correct way, because Y is only the negated
version of X.

> Signal 1 on a blue wire or signal 2 on a red wire.
One question in advance: are those signals synchronous to the FPGA
clock?

> Signal 1 on a blue wire or signal 2 on a red wire.
And you simply can connect them to one input without resulting in a bus
collision? Because when the blue wire drives a 0 and the red drives a 1
then what is the result? 0.5?

So if you have 2 wires you must do some "or"ing. Simplest way would be a
wired or with diodes or an open colletor driver.

But far more simple would be to connect the red wire to one input and
the blue to another input. And then it is very simple to determine on
which one the action is going on.

If this is a school homework, then lets say on 1 wire can show up 2
different pulse trains of type 1 and 2. In between those pulse trains at
least 48 clock cycles of 0 will show up.
Then its easy: set a timeout to 5..47 clock cycles and then start
counting the cycle of the next pulse. When its 3 then set x to 0. When
its 4 then set X to 1.
And as already mentioned: Y is simply the negation of X.

: Edited by Moderator

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Hi again, thanks a lot for the help so far. It's really appreciated!

Indeed these signal are synchronous to the clock of the fpga.

Either the red wire will be connected, or the blue wire. There will be
no situation these two signals arrive both at input A.

Your last description (besides this being a hobby project, not a school
project haha) is a correct one of the problem. I think I'll be able to
count the pulses and thus have the fpga "recognise" whether the "red
wire" with type 1 phlses or the "blue wire" with type 2 pulses is
connected.

The thing is... I can't really figure out how to set the output of X
forever high (keep the LED on) when type 1 pulses are detected for
example. I'm struggling to find what I should use to achieve that.

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Joey O. wrote:
> Either the red wire will be connected, or the blue wire. There will be
> no situation these two signals arrive both at input A.
So I would write two state machines:
FSM1 is for detecting the signal on red wire and
FSM2 is for detecting if you have taken the blue pill^W wire.

If you want to detect the series of bit "1010" then I would use four
states.
And a construct that looks something like this:
 1 switch( state):  2  case IDLE: if( input_bit = '1') state <= BIT0_OK; LED <= off;  3  case BIT0_OK: if( input_bit = '0') state <= BIT1_OK; LED <= off;  4  case BIT1_OK: if( input_bit = '1') state <= BIT2_OK; LED <= off;  5  case BIT2_OK: if( input_bit = '0') state <= IDLE; LED <= on;  6 end case;