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Forum: FPGA, VHDL & Verilog UART, FPGA VHDL


von Lukáš K. (Company: Stu) (kalajkak)


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Hello, I have a problem and I'm asking for help. I want to implement 
this code on the nexys 50 a7 ​​board. The idea of ​​how the board should 
work is that if I enter an eight-bit number on the switch, the segment 
display will show me what works. But when you click the button where the 
rd_uart variable is, nothing happens. it should be downloaded to the PC 
through putty. When typing on the keyboard, it should be displayed on 
the segment board, but only the tx light on the board flashes, but the 
rx vbc led does not flash, do you know where the problem is? I am 
sending a link to gifthub. : 
https://github.com/KrizLuk0/digital-electronics1/tree/main/UART_FPGA/project_U25

von Rick D. (rickdangerus)


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Divide your problem and debug:
- build an UART test transmitter to transmit a known pattern every e.g. 
100 ms
- if the tx works connect a counter/fsm to the transmitter and send a 
more complex pattern (e.g. 1-2-3-4-...)
- if the counter/fsm output is the same as you expect it, connect your 
keyboard to the fsm...

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Lukáš K. wrote:
> nothing happens
Your task sounds reasonably simple. Your solution looks incredible 
complicated. Why the heck do you need a fifo here? All interaction ist 
done by humans, so it is really sllllllooooowwwwwww regarding the 50MHz 
FPGA.

Lukáš K. wrote:
> if I enter an eight-bit number on the switch
What switch?
> the segment display will show me what works.
In what manner?
> But when you click the button
Which one?
> the button where the rd_uart variable is
???
> it
What ist "it"?
> should be downloaded to the PC through putty.
Putty is a software running on the PC. So maybe it should be received 
and visualized by Putty.
> When typing on the keyboard
What keayboard?
> it should be displayed on the segment board
In what manner?

So you want do display 2 informations on the 7seg display: the switches 
and the RX value? So: what has priority on the 7seg display?


I understand your description this way:
- from FPGA to PC
1. you enter some binary code on the dip siwtches
2. this code is displayed on the 7seg display (in hex? or decimal?)
3. when you press a button the code is sent via async serial (and 
afterwards somehow displayed on the PC Screen)
- from PC to FPGA
4. when you hit a key on the PC keyboard, some (ASCII?) code is sent via 
serial
5. the FPGA receives the data and shows it in some manner on the 7seg 
display

Is that correct?

von Lukáš K. (Company: Stu) (kalajkak)


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Yes, exactly as you describe, but the implementation does not work

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Lukáš K. wrote:
> but the implementation does not work
Split up the whole job in a TX and a RX section like Rick D. already 
advised.

What about simulation? The simulator is the debugger for your VHDL 
design. Do you have a test bench? What does it look like?

von Lukáš K. (Company: Stu) (kalajkak)


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I'm not sure if I understand correctly. Are you saying that I should 
separate the FIFO because it's unnecessary? Then, can I connect the 
output from RX (DOUT) directly to the segment display? And similarly, 
connect the switches directly to TX?

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Lukáš K. wrote:
> Are you saying...
Correct, thats would be my direction. Why using a fifo when nothing is 
stopping you from writing the display whenever you want. An adjustment 
of a new value takes longer for sure than sending the last value.

But as said: simulate your design before going on hardware.

Have a look at my RS232 implementation. Think about it and why it needs 
much less lines of code than yours:
http://www.lothar-miller.de/s9y/categories/42-RS232

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