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Forum: FPGA, VHDL & Verilog help - multi-driven \\ clocked by two different clocks


von DANIEL (Guest)


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First I would like to thank everyone who always helping (=, even if I am 
not always clear.
I had a lot of trouble creating a system, I'm trying to make it start 
working once until she finish working. The system needs to wait for 
external signal ' ' in order to work one more tw

When I write two different independent if conditions, then an error 
message comes out (p1 code) : [Synth 8-6859] multi-driven net on pin 
U4/chek with 1st driver pin 'U4/chek_reg__0/Q' 
["C:/Users/danie/Desktop/FinalProject/FinalProject/FinalProject.srcs/sou 
rces_1/new/eieo.vhd":66]

(p1 code)
1
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity eieo is
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    Port ( 
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           Tenb : in STD_LOGIC;
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              clk : in std_logic;
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             UPDOWN : in STD_LOGIC;
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             startcountenb : in std_logic; 
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           eo : out STD_LOGIC;
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           ei : out STD_LOGIC);
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end eieo;
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architecture Behavioral of eieo is
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signal chek : std_logic:='0';
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signal counter : integer range 0 to 100000000:=0;
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type state_type is(s1, s2, s3, s4);
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signal state : state_type :=s1;
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constant n1 : integer :=4001;
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constant n2: integer :=3001;
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constant n3 : integer :=4001;
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constant n4 : integer  :=2557011;
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signal tempoe : std_logic:='0';
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signal tempie : std_logic:='0';
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begin
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process(clk,chek,Tenb,UPDOWN,state) begin
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if( UPDOWN='1') then 
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    if(falling_edge(Tenb)) then 
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        chek<='1'; end if;
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----------&&&&&&&&&&&&&&&&&&&&&(((((((----------
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--else  
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end if; 
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----------&&&&&&&&&&&&&&&&&&&&&(((((((----------    
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if(rising_edge(clk) ) then 
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if(chek='1') then 
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counter<=counter+1;
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case state is 
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    when s1 => if( counter=n1) then tempie<=not(tempie);
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                                      tempoe<='0'; 
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                                      counter<=0;
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                                      state<=s2;
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                                      end if;
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    when s2 => if( counter=n2) then tempie<=not(tempie);
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                                      tempoe<='0'; 
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                                      counter<=0;
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                                      state<=s3;
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                                      end if;
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    when s3 => if( counter=n3) then tempoe<=not(tempoe);
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                                      tempie<='0';
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                                      counter<=0;
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                                      state<=s4; 
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                                      end if;
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    when s4 => if( counter=n4) then tempoe<=not(tempoe);
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                                     tempie<='0'; 
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                                     counter<=0;
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----------&&&&&&&&&&&&&&&&&&&&&(((((((-----------
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                                       chek<='0';  
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----------&&&&&&&&&&&&&&&&&&&&&(((((((-----------  
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                                     state<=s1; 
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                                      end if;
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end case; 
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else 
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tempie<='0';
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tempoe<='0'; 
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end if;
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end if; 
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----------&&&&&&&&&&&&&&&&&&&&&(((((((-----------
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--end if;
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----------&&&&&&&&&&&&&&&&&&&&&(((((((----------
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end process;
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ei<=tempie;
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eo<=tempoe;
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end Behavioral;



 When I write the " if's" under the same condition,  I get another error 
message (p2 code) : [Synth 8-5787] Register chek_reg in module eieo is 
clocked by two different clocks in the same process. This may cause 
simulation mismatches and synthesis errors. Consider using different 
process statements 
["C:/Users/danie/Desktop/FinalProject/FinalProject/FinalProject.srcs/sou 
rces_1/new/eieo.vhd":66]

(p2 code)
1
library IEEE;
2
use IEEE.STD_LOGIC_1164.ALL;
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entity eieo is
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    Port ( 
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           Tenb : in STD_LOGIC;
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              clk : in std_logic;
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             UPDOWN : in STD_LOGIC;
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             startcountenb : in std_logic; 
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           eo : out STD_LOGIC;
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           ei : out STD_LOGIC);
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end eieo;
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architecture Behavioral of eieo is
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signal chek : std_logic:='0';
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signal counter : integer range 0 to 100000000:=0;
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type state_type is(s1, s2, s3, s4);
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signal state : state_type :=s1;
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constant n1 : integer :=4001;
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constant n2: integer :=3001;
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constant n3 : integer :=4001;
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constant n4 : integer  :=2557011;
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signal tempoe : std_logic:='0';
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signal tempie : std_logic:='0';
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begin
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process(clk,chek,Tenb,UPDOWN,state) begin
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if( UPDOWN='1') then 
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    if(falling_edge(Tenb)) then 
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        chek<='1'; end if;
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----------&&&&&&&&&&&&&&&&&&&&&(((((((----------
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else  
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--end if; 
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----------&&&&&&&&&&&&&&&&&&&&&(((((((----------    
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if(rising_edge(clk) ) then 
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if(chek='1') then 
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counter<=counter+1;
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case state is 
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    when s1 => if( counter=n1) then tempie<=not(tempie);
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                                      tempoe<='0'; 
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                                      counter<=0;
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                                      state<=s2;
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                                      end if;
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    when s2 => if( counter=n2) then tempie<=not(tempie);
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                                      tempoe<='0'; 
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                                      counter<=0;
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                                      state<=s3;
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                                      end if;
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    when s3 => if( counter=n3) then tempoe<=not(tempoe);
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                                      tempie<='0';
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                                      counter<=0;
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                                      state<=s4; 
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                                      end if;
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    when s4 => if( counter=n4) then tempoe<=not(tempoe);
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                                     tempie<='0'; 
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                                     counter<=0;
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----------&&&&&&&&&&&&&&&&&&&&&(((((((-----
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                                       chek<='0';  
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----------&&&&&&&&&&&&&&&&&&&&&(((((((-----------                   
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                                     state<=s1; 
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                                      end if;
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end case; 
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else 
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tempie<='0';
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tempoe<='0'; 
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end if;
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end if; 
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----------&&&&&&&&&&&&&&&&&&&&&(((((((-----------
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end if;
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----------&&&&&&&&&&&&&&&&&&&&&(((((((----------
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end process;
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ei<=tempie;
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eo<=tempoe;
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end Behavioral;

What do you do in such cases, I didn't find any mention of it anywhere.

von Daniel C. (Company: NON) (r_daniel)



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Pictures of the system. I'm trying to get eieo to renew itself ) wtih 
chek<='0' and chek<='1';.

: Edited by User
von Dussel (Guest)


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You correctly used the vhdl formatting tags, but could you attach the 
code as vhdl file (correctly formatted)? The vhdl formatting is broken 
here, thus the code is difficult to read.

I suspect the problem might be the triggering on falling and rising 
edge. UPDOWN is a signal, so it might change during runtime and I don't 
know how and if this could be synthesised.

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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DANIEL wrote:
> What do you do in such cases
Write a clocked process as it is printed in any book. Or simply have a 
close look at the synthesizers user manual how a  synchronous has to be 
written.

To keep things simple: use only one clock and only one edge of it. In 
the whole design.

And one additional hint: check your sensitivity lists. When the 
sensitivity list is wrong, then the simulation will not match the real 
hardware.

von Daniel C. (Company: NON) (r_daniel)


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I'm aware of the problem, I understand why it's not right in a simple 
way, it's not possible to turn the action into code

von Daniel C. (Company: NON) (r_daniel)


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All other components depend on the signal eo ei that the system produces

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