First I would like to thank everyone who always helping (=, even if I am
not always clear.
I had a lot of trouble creating a system, I'm trying to make it start
working once until she finish working. The system needs to wait for
external signal ' ' in order to work one more tw
When I write two different independent if conditions, then an error
message comes out (p1 code) : [Synth 8-6859] multi-driven net on pin
U4/chek with 1st driver pin 'U4/chek_reg__0/Q'
["C:/Users/danie/Desktop/FinalProject/FinalProject/FinalProject.srcs/sou
rces_1/new/eieo.vhd":66]
(p1 code)
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 | -- Uncomment the following library declaration if using
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5 | -- arithmetic functions with Signed or Unsigned values
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6 | --use IEEE.NUMERIC_STD.ALL;
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7 |
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8 | -- Uncomment the following library declaration if instantiating
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9 | -- any Xilinx leaf cells in this code.
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10 | --library UNISIM;
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11 | --use UNISIM.VComponents.all;
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12 |
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13 | entity eieo is
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14 | Port (
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15 | Tenb : in STD_LOGIC;
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16 | clk : in std_logic;
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17 | UPDOWN : in STD_LOGIC;
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18 | startcountenb : in std_logic;
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19 | eo : out STD_LOGIC;
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20 | ei : out STD_LOGIC);
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21 | end eieo;
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22 |
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23 | architecture Behavioral of eieo is
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24 | signal chek : std_logic:='0';
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25 | signal counter : integer range 0 to 100000000:=0;
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26 | type state_type is(s1, s2, s3, s4);
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27 | signal state : state_type :=s1;
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28 | constant n1 : integer :=4001;
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29 | constant n2: integer :=3001;
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30 | constant n3 : integer :=4001;
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31 | constant n4 : integer :=2557011;
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32 | signal tempoe : std_logic:='0';
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33 | signal tempie : std_logic:='0';
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34 |
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35 |
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36 | begin
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37 |
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38 |
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39 |
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40 |
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41 | process(clk,chek,Tenb,UPDOWN,state) begin
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42 |
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43 | if( UPDOWN='1') then
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44 | if(falling_edge(Tenb)) then
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45 | chek<='1'; end if;
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46 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((----------
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47 | --else
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48 | end if;
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49 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((----------
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50 |
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51 | if(rising_edge(clk) ) then
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52 |
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53 | if(chek='1') then
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54 |
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55 | counter<=counter+1;
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56 |
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57 | case state is
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58 |
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59 | when s1 => if( counter=n1) then tempie<=not(tempie);
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60 | tempoe<='0';
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61 | counter<=0;
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62 | state<=s2;
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63 |
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64 | end if;
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65 |
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66 | when s2 => if( counter=n2) then tempie<=not(tempie);
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67 | tempoe<='0';
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68 | counter<=0;
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69 | state<=s3;
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70 | end if;
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71 |
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72 | when s3 => if( counter=n3) then tempoe<=not(tempoe);
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73 | tempie<='0';
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74 | counter<=0;
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75 | state<=s4;
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76 | end if;
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77 |
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78 | when s4 => if( counter=n4) then tempoe<=not(tempoe);
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79 | tempie<='0';
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80 | counter<=0;
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81 |
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82 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((-----------
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83 | chek<='0';
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84 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((-----------
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85 |
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86 | state<=s1;
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87 | end if;
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88 | end case;
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89 | else
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90 | tempie<='0';
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91 | tempoe<='0';
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92 | end if;
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93 | end if;
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94 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((-----------
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95 | --end if;
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96 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((----------
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97 | end process;
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98 | ei<=tempie;
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99 | eo<=tempoe;
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100 | end Behavioral;
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When I write the " if's" under the same condition, I get another error
message (p2 code) : [Synth 8-5787] Register chek_reg in module eieo is
clocked by two different clocks in the same process. This may cause
simulation mismatches and synthesis errors. Consider using different
process statements
["C:/Users/danie/Desktop/FinalProject/FinalProject/FinalProject.srcs/sou
rces_1/new/eieo.vhd":66]
(p2 code)
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 |
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5 |
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6 | entity eieo is
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7 | Port (
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8 | Tenb : in STD_LOGIC;
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9 | clk : in std_logic;
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10 | UPDOWN : in STD_LOGIC;
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11 | startcountenb : in std_logic;
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12 | eo : out STD_LOGIC;
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13 | ei : out STD_LOGIC);
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14 | end eieo;
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15 |
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16 | architecture Behavioral of eieo is
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17 | signal chek : std_logic:='0';
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18 | signal counter : integer range 0 to 100000000:=0;
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19 | type state_type is(s1, s2, s3, s4);
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20 | signal state : state_type :=s1;
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21 | constant n1 : integer :=4001;
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22 | constant n2: integer :=3001;
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23 | constant n3 : integer :=4001;
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24 | constant n4 : integer :=2557011;
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25 | signal tempoe : std_logic:='0';
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26 | signal tempie : std_logic:='0';
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27 |
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28 |
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29 | begin
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30 |
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31 |
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32 |
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33 |
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34 | process(clk,chek,Tenb,UPDOWN,state) begin
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35 |
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36 | if( UPDOWN='1') then
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37 | if(falling_edge(Tenb)) then
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38 | chek<='1'; end if;
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39 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((----------
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40 | else
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41 | --end if;
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42 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((----------
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43 |
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44 | if(rising_edge(clk) ) then
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45 |
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46 | if(chek='1') then
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47 |
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48 | counter<=counter+1;
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49 |
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50 | case state is
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51 |
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52 | when s1 => if( counter=n1) then tempie<=not(tempie);
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53 | tempoe<='0';
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54 | counter<=0;
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55 | state<=s2;
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56 |
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57 | end if;
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58 |
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59 | when s2 => if( counter=n2) then tempie<=not(tempie);
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60 | tempoe<='0';
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61 | counter<=0;
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62 | state<=s3;
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63 | end if;
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64 |
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65 | when s3 => if( counter=n3) then tempoe<=not(tempoe);
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66 | tempie<='0';
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67 | counter<=0;
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68 | state<=s4;
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69 | end if;
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70 |
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71 | when s4 => if( counter=n4) then tempoe<=not(tempoe);
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72 | tempie<='0';
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73 | counter<=0;
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74 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((-----
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75 | chek<='0';
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76 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((-----------
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77 | state<=s1;
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78 | end if;
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79 | end case;
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80 | else
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81 | tempie<='0';
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82 | tempoe<='0';
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83 | end if;
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84 | end if;
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85 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((-----------
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86 | end if;
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87 | ----------&&&&&&&&&&&&&&&&&&&&&(((((((----------
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88 | end process;
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89 | ei<=tempie;
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90 | eo<=tempoe;
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91 | end Behavioral;
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What do you do in such cases, I didn't find any mention of it anywhere.