Quartus Prime Verilog error Node "X" is missing source

Dear all,

I have a newbie question on Verilog. I am using Quartus Prime (Lite Edition) to write some Verilog code for my Arduino MKRVIDOR 4000 (Arduino board with FPGA); my goal is to get communication between the CPU and FPGA working using Florian Zachs's JTAG interface (https://github.com/HerrNamenlos123/JTAG_Interface). I use a standard MKRVIDOR4000_top.v template (containing all the definitions of the I/O signals etc.) that includes user.v that has my own code. The template is attached for reference but the error is in the code below.

What I can't get to synthesize, for reasons I don't understand, is to change behaviour of an input-output mapping between two digital pins shared between the CPU and FPGA based on the contents of a register that can be written to using the JTAG interface. Either the FPGA copies the digital signal it receives on D5 to D6, or it inverts the signal. I want to change this behaviour using a command issued via JTAG.

This is my code:

1

// define register used to communicate from microcontroller to FPGA using JTAG interface

2

reg [31:0] COMMAND;

3

4

// 1-bit registers

5

reg spike_in;

6

reg spike_out;

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reg state_var;

8

9

// wOSC_CLK is the clock input signal used by the JTAG interface

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JTAG_Interface  b2v_inst1(

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 .iCLK(wOSC_CLK),

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 .iREAD_0(COMMAND)

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 );

14

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// either copy or negate input pin D[5] to output pin D[6]

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always @(posedge wOSC_CLK) 

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begin

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 spike_in <= bMKR_D[5];

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 spike_out <= (state_var == 1'b1) ? spike_in : ~spike_in;

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 bMKR_D[6] <= spike_out;

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end

22

23

// react on JTAG change of COMMAND register (only msb is relevant)

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always @(COMMAND) 

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begin

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 state_var <= COMMAND[31];

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end

Quartus doesn't accept this code, complaining "12009 Node "spike_out" is missing source". I don't understand why this is the case, although I assume that the conditional assignment to spike_out is to blame, because the circuit synthesizes when I make this unconditional on state_var. I hope someone can enlighten me why this is the case and how the desired behaviour could be achieved.