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Forum: FPGA, VHDL & Verilog What is the error in the code below and why does vivado output u


von Engin S. (Company: Yildiz Technical University) (enginsun)


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I don't see any sintax errors but the value of both my outputs is "u". 
why do you think?


1
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_unsigned.all;
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entity DDR is
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  port (
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      ALARM_TIME     : in std_logic_vector (3 downto 0);
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      CURRENT_TIME   : in std_logic_vector (3 downto 0);
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      SHOW_A      : in std_logic;
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      -----
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      DISPLAY      : out std_logic_vector (6 downto 0);
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      SOUND_ALARM    : out std_logic
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    );
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end DDR;
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architecture RTL of DDR is
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  signal DISP_CURRENT  : std_logic_vector (6 downto 0);
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  signal DISP_ALARM  : std_logic_vector (6 downto 0);
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  begin
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    DISP_CURRENT      <=   "0111111" when CURRENT_TIME="0000" else --0
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              "0000110" when CURRENT_TIME="0001" else --1
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              "1011011" when CURRENT_TIME="0010" else --2
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              "1001111" when CURRENT_TIME="0011" else --3
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              "1100110" when CURRENT_TIME="0100" else --4
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              "1101101" when CURRENT_TIME="0101" else --5
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              "1111101" when CURRENT_TIME="0110" else --6
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              "0000111" when CURRENT_TIME="0111" else --7
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              "1111111" when CURRENT_TIME="1000" else --8
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              "1101111" when CURRENT_TIME="1001" else --9
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              "1100011"   ;      
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    DISP_ALARM       <=   "0111111" when ALARM_TIME="0000" else --0
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              "0000110" when ALARM_TIME="0001" else --1
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              "1011011" when ALARM_TIME="0010" else --2
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              "1001111" when ALARM_TIME="0011" else --3
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              "1100110" when ALARM_TIME="0100" else --4
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              "1101101" when ALARM_TIME="0101" else --5
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              "1111101" when ALARM_TIME="0110" else --6
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              "0000111" when ALARM_TIME="0111" else --7
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              "1111111" when ALARM_TIME="1000" else --8
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              "1101111" when ALARM_TIME="1001" else --9
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              "1100011"   ;            
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  process (DISP_ALARM, SHOW_A, DISP_CURRENT) is
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    begin
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      if SHOW_A = '1' then
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        DISPLAY <= DISP_ALARM;
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      else 
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        DISPLAY <= DISP_CURRENT;
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      end if;
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  end process;
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  --DISPLAY     <= DISP_ALARM when SHOW_A = '1' else DISP_CURRENT; 
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  SOUND_ALARM   <= '1' when DISP_ALARM = DISP_CURRENT else '0';
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end RTL;


TESTBENCH
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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--library work;
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--use work.P_DISP1.all;
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entity t_DDR is
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end t_DDR;
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architecture RTL of t_DDR is
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  component DDR is
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    port (
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        ALARM_TIME     : in std_logic_vector (3 downto 0);
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        CURRENT_TIME   : in std_logic_vector (3 downto 0);
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        SHOW_A      : in std_logic;
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        -----
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        DISPLAY      : out std_logic_vector (6 downto 0);
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        SOUND_ALARM    : out std_logic
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      );
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  end component;
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    signal ALARM_TIME     : std_logic_vector (3 downto 0);
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    signal CURRENT_TIME   : std_logic_vector (3 downto 0);
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    signal SHOW_A      : std_logic;
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    signal DISPLAY      : std_logic_vector (6 downto 0);
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    signal SOUND_ALARM    : std_logic;
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    signal DISP_ALARM    : std_logic_vector (6 downto 0);
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    signal DISP_CURRENT    : std_logic_vector (6 downto 0);
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    begin
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    uut : DDR port map
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      (
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        ALARM_TIME    => ALARM_TIME,
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        CURRENT_TIME   => CURRENT_TIME,
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        SHOW_A       => SHOW_A,
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        DISPLAY       => DISPLAY,
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        SOUND_ALARM   => SOUND_ALARM
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      );
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    process
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      begin
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        ALARM_TIME     <= "0110";
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        CURRENT_TIME   <= "1001";
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        SHOW_A       <= '1';
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        wait for 20 ns;
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--        DISP1(DISPLAY);
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        ALARM_TIME     <= "0111";
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        CURRENT_TIME   <= "1000";
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        SHOW_A       <= '0';
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        wait for 20 ns;
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--        DISP1(DISPLAY);
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        ALARM_TIME     <= "0011";
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        CURRENT_TIME   <= "0000";
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        SHOW_A       <= '1';
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        wait for 20 ns;
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--        DISP1(DISPLAY);
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        ALARM_TIME     <= "0111";
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        CURRENT_TIME   <= "0110";
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        SHOW_A       <= '0';
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        wait for 20 ns;
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--        DISP1(DISPLAY);
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        ALARM_TIME     <= "1001";
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        CURRENT_TIME   <= "1001";
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        SHOW_A       <= '1';
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        wait for 20 ns;
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--        DISP1(DISPLAY);    
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      wait;
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    end process;
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  end RTL;

: Moved by Moderator
von Gustl B. (-gb-)


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Engin S. wrote:
> both my outputs

DISP_ALARM
and
DISP_CURRENT
are not connected in t_DDR.

The other signals show valid signals.

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