What are the reasons that the system I designed will work exactly in the simulation, at the same time you will not see errors, but after burning the system will not work on the board. What do you start looking for in the code at such a stage?
There can be plenty of errors you will not see in simulation. Your simulation looks like something with SPI or I2C. So you have to build the external slave device in the testbench as well. With correct timing and startup configuration. Often some signals just don't match the testbench. Clock frequency higher or lower, ... But you may show more code. Just upload all your HDL and the testbench so we can simulate as well.
Daniel C. wrote: > What are the reasons The usual way to get there is by ignoring the warnings and infos reported by the toolchain when generating the bitstream file. > What do you start looking for The report files: are there any obscure warnings or infos? And the RTL schematic: does the synthesizers schematic look like your idea?