N:1 MUX with 2:1 MUXs, VHDL

Hi ! So I'm trying to write VHDL code to implement an N:1 MUX with 2:1 MUXs. At the beginning I used a process but the compiler quickly pointed out to me that we can't use port map inside a process So I omitted the process and turn the variables into signals and I got this:

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.std_logic_unsigned.all;        

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use ieee.numeric_std.all;            

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entity MUX8_1 is

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  generic (

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      N : integer := 8;  -- N vers 1

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      C : integer := 3   -- Signaux de contrôle

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    );

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  port (

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    E : IN std_logic_vector(N-1 downto 0);

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    CTRL : IN std_logic_vector(C-1 downto 0);

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    S : OUT std_logic

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  );

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end MUX8_1;

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architecture MUX8_1_arc of MUX8_1 is

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--generic map (

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--       N => 8,

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--       C => 3

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--  )

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component MUX2_1 is

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  port (

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    E :  IN std_logic_vector (1 downto 0);

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    SLCT : IN std_logic; --avec 1 downto 0, la conversion

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    S : OUT std_logic               -- ne peut se faire

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  );

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end component;

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  signal L : integer := N;

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  signal a : integer := 0;

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  signal E1 : std_logic_vector(N-1 downto 0);

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  signal T1 : std_logic_vector(N-1 downto 0) := E;

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  signal T : std_logic;

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begin

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  Controle : for j in 0 to C-1 generate

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    L <= L/2;

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    a <= 0;

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    E1 <= T1;

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    T1 <= (others => '0');

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    Entree : for i in 0 to 2*L-1 generate

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      if (a mod 2 = 0) then

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        MUX : entity work.MUX2_1 port map(E1(2*L-1-i downto 2*L-2-i), CTRL(j), T);

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        T1 <= T1&T;

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      end if;

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      a <= a + 1;

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    end generate;

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  end generate;

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end MUX8_1_arc;

And here are the errors and warnings that I got:

** Error: C:\Users\loune\OneDrive\Bureau \EE\S2\MSCL\Devoir Maison 1\Ex1_N.vhd(53): illegal concurrent statement. ** Error: C:\Users\loune\OneDrive\Bureau \EE\S2\MSCL\Devoir Maison 1\Ex1_N.vhd(54): (vcom-1450) Actual (slice name) for formal "E" is not a static signal name.

** Warning: C:\Users\loune\OneDrive\Bureau \EE\S2\MSCL\Devoir Maison 1\Ex1_N.vhd(51): (vcom-1147) Range in parameter specification of FOR GENERATE must be static.

** Warning: C:\Users\loune\OneDrive\Bureau \EE\S2\MSCL\Devoir Maison 1\Ex1_N.vhd(41): (vcom-1013) Initial value of "T1" depends on value of signal "E".

** Warning: C:\Users\loune\OneDrive\Bureau \EE\S2\MSCL\Devoir Maison 1\Ex1_N.vhd(38): Nonresolved signal 'L' may have multiple sources. Drivers:

C:\Users\loune\OneDrive\Bureau \EE\S2\MSCL\Devoir Maison 1\Ex1_N.vhd(45):Conditional signal assignment line__45

** Warning: C:\Users\loune\OneDrive\Bureau \EE\S2\MSCL\Devoir Maison 1\Ex1_N.vhd(39): Nonresolved signal 'a' may have multiple sources. Drivers:

C:\Users\loune\OneDrive\Bureau \EE\S2\MSCL\Devoir Maison 1\Ex1_N.vhd(57):Conditional signal assignment line__57

C:\Users\loune\OneDrive\Bureau \EE\S2\MSCL\Devoir Maison 1\Ex1_N.vhd(46):Conditional signal assignment line__46

Any help is welcome.