# Forum: FPGA, VHDL & Verilog Pipeline circuit

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Hi, I need to write the VHDL code of the following pipeline circuit:
The circuit receives 2 control signals and two input signal of n bit and
A+B if c0=c1=0
-A-B if c0=c1=1
A-B if c1=0 and c0=0
-A+B if c1=1 and c0=0
I have written the following diagram circuits but I don't know if I need
to put registers between the two adders.
Thank you for the answers.

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What pipeline?

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Input:

I need to write the VHDL code of the following pipeline circuit:
The circuit receives 2 control signals and two input signal of n bit and
A+B if c0=c1=0
-A-B if c0=c1=1
A-B if c1=0 and c0=0
-A+B if c1=1 and c0=0

To implement this circuit in VHDL, you will need to use an if-else
statement to determine the output based on the values of the control
signals c0 and c1. Here is an example of how you can write the VHDL code
for this circuit:

 1 library ieee;  2 use ieee.std_logic_1164.all;  3 4 entity pipeline_circuit is  5  port (  6  c0 : in std_logic;  7  c1 : in std_logic;  8  A : in std_logic_vector(n-1 downto 0);  9  B : in std_logic_vector(n-1 downto 0);  10  result : out std_logic_vector(n-1 downto 0)  11  );  12 end pipeline_circuit;  13 14 architecture behavioral of pipeline_circuit is  15 begin  16  process(c0, c1, A, B)  17  begin  18  if (c0 = '0' and c1 = '0') then  19  result <= A + B;  20  elsif (c0 = '1' and c1 = '1') then  21  result <= -A - B;  22  elsif (c1 = '0' and c0 = '0') then  23  result <= A - B;  24  elsif (c1 = '1' and c0 = '0') then  25  result <= -A + B;  26  else  27  result <= (others => 'Z'); -- default value for result  28  end if;  29  end process;  30 end behavioral; 

This code defines an entity called "pipeline_circuit" with four inputs
(c0, c1, A, and B) and one output (result). The output is determined by
the values of the control signals c0 and c1 using the if-else statement
in the process.

I hope this helps! Let me know if you have any questions.