I'm creating a combinational multiplier and I wrote it in Verilog, but I'm having an unusual error. My simulation tool runs the code ok with testbench, but the logic synthesis tool shows the error "Internal assertion failure. (VER-37)". I tested and the error is found on line 23, specifically in the $RTOI function, but I didn't find a way to fix it. I'm usign Synopsis tools. All i want is get the rounded square of a number and use it to build my index.
Internal errors usually mean that there is really a bug in the synthesis tool. Can you try another tool, like Vivado? I don't understand the details of your code, but there is no reason why $rtoi() should fail here. Instead of $rtoi() you could use a simple integer casting just to see if that passes the synthesis. And then you could write your own version of $rtoi() and file a ticket at Synopsys.