Hi,
I have a multi stage process and each step need some time. I want to
create some sequencer which is able to generate positive edges at
certain intervals and at the end /beginning of the cycle reset this
signals.
Not that complicated, I thought, but I fail totally.
If I do it in hardware:
Counter, 11 bit wide, increments at each clock cycle, some comparators,
comparing the actual count against a constant and if equal, set the
output for one clock cycle, ==> get my positive edge.
If I do it in Verilog:
1 |
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2 | always @ (negedge clk)
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3 | begin
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4 | if ( reset )
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5 | reg_step = 3'd0;
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6 | else
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7 | if ( reg_step < 8'd240 || reg_sel != 3'd7 ) reg_step <= ( reg_step == 8'd240 ) ? 8'd0 : reg_step + 8'd1;
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8 | end
|
9 |
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10 | // Generate stage clocks and incremet wave index
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11 | always @ (posedge clk)
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12 | if ( reset )
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13 | begin
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14 | reg_sel = 3'd7;
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15 | reg_accu_clk = 0;
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16 | reg_lut_clk = 0;
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17 | reg_mix_clk = 0;
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18 | end
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19 | else
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20 | /*
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21 | case ( reg_step )
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22 | 8'd2:
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23 | begin
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24 | reg_sel = reg_sel + 3'd1;
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25 | reg_accu_clk = 0;
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26 | reg_lut_clk = 0;
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27 | reg_mix_clk = 0;
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28 | end
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29 | 8'd10:
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30 | reg_accu_clk <= 1;
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31 | 8'd20:
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32 | reg_lut_clk <= 1;
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33 | 8'd200: // 100 .. fails, 150 works, 150-20 = 130 * 2.5ns = 325 ns for the 12 bit sin_lut
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34 | reg_mix_clk <= 1;
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35 | endcase
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36 | */
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37 |
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38 | begin
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39 | if ( reg_step == 8'd2 )
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40 | begin
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41 | reg_sel = reg_sel + 3'd1;
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42 | reg_accu_clk = 0;
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43 | reg_lut_clk = 0;
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44 | reg_mix_clk = 0;
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45 | end
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46 |
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47 | if ( reg_step == 8'd10 ) reg_accu_clk <= 1;
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48 |
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49 | if ( reg_step == 8'd20 ) reg_lut_clk <= 1;
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50 |
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51 | if ( reg_step == 8'd200 ) reg_mix_clk <= 1;
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52 | end
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I tried two options.
In the simulation, everything is fine.
In real nothing works.
I use the RTL viewer and it was funny to see what the compiler thought
that I want to do.
Can some body help me and tell me, how I can implement such a simple
sequencer in Verilog or should I better start drawing a schematic using
primitives in my Quartus Prime?
What is the target:
At negedge, the counter advances/resets. At the posedge (the counter
value is stable I guess ...) the counter value is compared with some
constants and if there is one found to be equal, the output is 1, 0
otherwise.
I get posedges at certain poits in time (relative to the start),
synchronized with the posedge of my clock.
Sorry about code formatting ..
With best regards
Gerhard
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