Puls generator

Gerhard K. (gerhardkreuzer) OP 2023-01-21 16:11 #7323656

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Hi, I have a multi stage process and each step need some time. I want to create some sequencer which is able to generate positive edges at certain intervals and at the end /beginning of the cycle reset this signals. Not that complicated, I thought, but I fail totally.

If I do it in hardware: Counter, 11 bit wide, increments at each clock cycle, some comparators, comparing the actual count against a constant and if equal, set the output for one clock cycle, ==> get my positive edge.

If I do it in Verilog:

always @ (negedge clk)

    begin

      if ( reset )

        reg_step = 3'd0;

        else

        if ( reg_step < 8'd240 || reg_sel != 3'd7 ) reg_step <= ( reg_step == 8'd240 ) ? 8'd0 : reg_step + 8'd1;

    end  

  // Generate stage clocks and incremet wave index

  always @ (posedge clk)

    if ( reset )

      begin

        reg_sel      = 3'd7;

        reg_accu_clk  =    0;

        reg_lut_clk    =    0;

        reg_mix_clk    =    0;  

    else

      case ( reg_step )

          begin

            reg_sel      = reg_sel + 3'd1;

            reg_accu_clk  = 0;

            reg_lut_clk    = 0;

            reg_mix_clk    = 0;  

          reg_accu_clk <= 1;

          reg_lut_clk   <= 1;          

        8'd200:                          // 100 .. fails, 150 works, 150-20 = 130 * 2.5ns = 325 ns for the 12 bit sin_lut

          reg_mix_clk  <= 1;

      endcase  

    begin

      if ( reg_step == 8'd2 ) 

        begin

          reg_sel      = reg_sel + 3'd1;

          reg_accu_clk  = 0;

          reg_lut_clk    = 0;

          reg_mix_clk    = 0;  

      if ( reg_step == 8'd10 )  reg_accu_clk  <= 1;

      if ( reg_step == 8'd20 )  reg_lut_clk  <= 1;

      if ( reg_step == 8'd200 ) reg_mix_clk  <= 1;

    end

I tried two options. In the simulation, everything is fine. In real nothing works.

I use the RTL viewer and it was funny to see what the compiler thought that I want to do.

Can some body help me and tell me, how I can implement such a simple sequencer in Verilog or should I better start drawing a schematic using primitives in my Quartus Prime?

What is the target: At negedge, the counter advances/resets. At the posedge (the counter value is stable I guess ...) the counter value is compared with some constants and if there is one found to be equal, the output is 1, 0 otherwise.

I get posedges at certain poits in time (relative to the start), synchronized with the posedge of my clock.

Sorry about code formatting ..

With best regards

Gerhard

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