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Forum: FPGA, VHDL & Verilog AXI stream FIFO


von Stanley (hmscosgrove)


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I am a newbies in VHDL, and currently still learning, could anyone 
kindly advise how i can start coding VHDL on Vivado a FIFO using AXI 
stream that receive a data-in with 64 Bytes containing hexadecimal : 
0xEEFFAAFFAAFFAAFFAAFFAA......
Do i need a Finite state machine to start with ? Pls advise, thanks in 
advance..
Stanley

von Gustl B. (-gb-)


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There are details missing:
AXI datawidth, desired FIFO depth, ...
You may use the Xilinx FIFO component. It comes free with VIVADO.

von Stanley (hmscosgrove)


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thx for the reply, T byte =64, fifo depth =32, yes i am aware Vivado can 
configure FIFO AXI steam, is there any website or tutorial that show 
this?
Pls reply soon, thanks. cosgrove.

von Gustl B. (-gb-)


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Did you search for more information?

If yes, then you must have stumbled across the userguide:

https://docs.xilinx.com/v/u/en-US/pg080-axi-fifo-mm-s

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