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Vhdl project: mini-router
von Luciana (luciana)

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I have a project about design and implementation of a mini router. I' ll 
share the source code I wrote and the design in Vivado. Can someone 
expalin why the design is organized in this way? Is it correct?

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-- -------------------------

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-- Libreria

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-- -------------------------

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library IEEE;

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use IEEE.std_logic_1164.all;

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use IEEE.numeric_std.all;

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-- -------------------------

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-- Entity 

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-- -------------------------

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entity mini_router is

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   port (

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         clk       : in  std_logic; 

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         reset     : in  std_logic; -- Reset asincrono attivo basso

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     data1     : in  std_logic_vector(9 downto 0); 

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     req1      : in  std_logic; 

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     grant1    : out std_logic;

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         data2     : in  std_logic_vector(9 downto 0); 

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     req2      : in  std_logic; 

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     grant2    : out std_logic;

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     data_out  : out std_logic_vector(7 downto 0); 

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     valid     : out std_logic

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        );

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end entity;

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-- -------------------------

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-- Architecture 

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-- -------------------------  

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architecture arch of mini_router is  

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-- Segnale per controllo req

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   signal request    : std_logic_vector (1 downto 0);  

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-- Segnali per controllo bit di parità

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   signal a          : std_logic; -- '1' se A < B altrimenti '0'

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   signal b          : std_logic; -- '1' se A = B altrimenti '0'  

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   signal c          : std_logic; -- '1' se A > B altrimenti '0'

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-- Segnale per applicazione dell'algoritmo Round Robin

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   signal r          : std_logic; 

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-- Comparatore per controllo sui bit di parità  

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  component comparator is

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     port (

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            A           : in std_logic_vector(1 downto 0); 

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            B           : in std_logic_vector(1 downto 0); 

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            A_less_B    : out std_logic; 

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            A_equal_B   : out std_logic;

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            A_greater_B : out std_logic      

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          );

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   end component;

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 begin

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  request     <= req1&req2;

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   COMPARATORE: comparator

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    port map ( 

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      A           => data1 (1 downto 0),

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      B           => data2 (1 downto 0),

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      A_less_B    => a,

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      A_equal_B   => b,

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      A_greater_B => c

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           );

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 mini_router: process(clk,reset)

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 begin

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   if reset = '0' then

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       data_out    <= (others => '0');

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     grant1      <= '0';

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     grant2      <= '0';   

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     valid       <= '0';

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     r           <= '0';

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   elsif rising_edge(clk) then

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 -- Un solo req è alto

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      if request = "10" then 

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       data_out <= data1(9 downto 2);

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         grant1   <= '1';

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       grant2   <= '0';

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       valid    <= '1';

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   elsif request = "01" then 

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         data_out <= data2(9 downto 2);

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         grant1   <= '0';

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       grant2   <= '1';

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       valid    <= '1';

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-- Entrambi i req sono bassi    

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     elsif request = "00" then  

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      data_out <= (others => '0');

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      grant1   <= '0';

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        grant2   <= '0';

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        valid    <= '0'; 

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-- Entrambi i req sono alti  

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   elsif request = "11" then

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-- Il link 1 ha maggiore priorità

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        if c='1' then

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           data_out  <= data1(9 downto 2);

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           grant1    <= '1';

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         grant2    <= '0';

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         valid     <= '1';

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-- Il link 2 ha maggiore priorità      

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        elsif a='1' then

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           data_out  <= data2(9 downto 2);

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         grant1    <= '0';

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         grant2    <= '1';

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         valid     <= '1';

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 -- Data conflict

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        elsif b='1' then  

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-- Applicazione dell'algoritmo Round Robin

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           if r = '0' then 

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              data_out  <= data1(9 downto 2);

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              grant1    <= '1';

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            grant2    <= '0';

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            valid     <= '1';

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              r         <= '1';

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           else 

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              data_out  <= data2(9 downto 2);

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          grant1    <= '0';

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            grant2    <= '1';

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            valid     <= '1';

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              r         <= '0';

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           end if;

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        end if;

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      end if; 

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    end if; 

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  end process;

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end architecture;


  


  




  

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