Hi everyone, I would like your help regarding the xdc file of a project 
for handling a double input ADC. For testing purposes, I'm testing only 
one input first, then I'll test both. When running Generate Bitstream I 
get the following error message.

Error: [DRC UCIO-1] Unconstrained Logical Port: 12 out of 22 logical 
ports have no user assigned specific location constraint (LOC). This may 
cause I/O contention or incompatibility with the board power or 
connectivity affecting performance, signal integrity or in extreme cases 
cause damage to the device or the components to which it is connected. 
To correct this violation, specify all pin locations. This design will 
fail to generate a bitstream unless all logical ports have a user 
specified site LOC constraint defined.  To allow bitstream creation with 
unspecified pin locations (not recommended), use this command: 
set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When 
using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add 
this command to a .tcl file and add that file as a pre-hook for 
write_bitstream step for the implementation run.  Problem ports: 
Dout[9:0], CLK, and CLK_out.




I hope to be able to connect the PYNQ Z2 with my Eval-Borad LTC2287 via 
the Pynq Z2's RPi inputs.