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Forum: FPGA, VHDL & Verilog Verilog JK - help pls


von Daniel C. (Company: NON) (r_daniel)



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What is the problem that signal is not defined? How do you define an 
initial value for the output?


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module JK_Latch(Q, Qbar, J, K, Enable);
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input J, K, Enable;
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output Q, Qbar;
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wire J_E, K_E;
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and(J_E, J, Enable, Qbar);
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and(K_E, K, Enable, Q);
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nor(Q, Qbar, K_E);
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nor(Qbar, Q, J_E);
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endmodule
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module TB_JK_Latch();
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wire q, qbar;
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reg j, k, e;
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JK_Latch JK0(q, qbar, j, k, e);
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initial
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begin
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    $monitor($time," j =%b, k=%b, q=%b, qbar=%b, enable=%b\n",j,k,q,qbar,e);
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    j=1; k=0; e=1;
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    #5 j=0; k=1;
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    #5 j=0; k=0;
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    #5 j=1; k=0;
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    #5 j=1; k=1;
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    #5 j=1; k=1; e=0;
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    #5 j=0; k=1;
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    #5 j=0; k=0;
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    #5 j=1; k=0;
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    #5 j=1; k=1;
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end
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endmodule

von Marc (vancouver)


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Daniel C. wrote:
> What is the problem that signal is not defined?

There is a permanent mutual dependency betwenn Q and Qbar that can not 
be overridden by the input signals. So, since Q and Qbar are undefined 
in the beginning, they remain undefined forever in the simulation. In 
real hardware, they would fall into a random state which is mainly 
determined by physical parameters of the technology.

> How do you define an
> initial value for the output?

By using the initial statement. But only in the simulation. initial will 
not synthesize. Or you could extend your design by a reset signal that 
forces Q or Qbar to a logic level.

I hope you are doing this just for learning and playing around in the 
simulator. In real hardware designs, you would avoid latches as far as 
possible. And if you really would need one, you would use a D-latch. And 
if you really really would need a JK-latch, you would never use a 
self-build combinatorial feedback latch but take a primitive from a 
vendor library or emulate it using a D-latch. Actually, since more than 
30 years, JK FFs and latches are used for stressing students, so unless 
you are a student, you should forget about JK type memories.

And please stop using gate primitives in your design. Use boolean 
expressions instead:

nor(Qbar, Q, J_E) is equivalent to
assign Qbar = ~(Q | J_E)

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