Daniel C. wrote:
What is the problem that signal is not defined?
There is a permanent mutual dependency betwenn Q and Qbar that can not be overridden by the input signals. So, since Q and Qbar are undefined in the beginning, they remain undefined forever in the simulation. In real hardware, they would fall into a random state which is mainly determined by physical parameters of the technology.
How do you define an
initial value for the output?
By using the initial statement. But only in the simulation. initial will not synthesize. Or you could extend your design by a reset signal that forces Q or Qbar to a logic level.
I hope you are doing this just for learning and playing around in the simulator. In real hardware designs, you would avoid latches as far as possible. And if you really would need one, you would use a D-latch. And if you really really would need a JK-latch, you would never use a self-build combinatorial feedback latch but take a primitive from a vendor library or emulate it using a D-latch. Actually, since more than 30 years, JK FFs and latches are used for stressing students, so unless you are a student, you should forget about JK type memories.
And please stop using gate primitives in your design. Use boolean expressions instead:
nor(Qbar, Q, J_E) is equivalent to
assign Qbar = ~(Q | J_E)
