# Forum: FPGA, VHDL & Verilog Verilog circuit

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i need to write this circuit in verilog.
Thanks.

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Well ... how are a, b and c connected at the bottom of the MUX? The left
input is b, then a and right is c. So 000 ... 111 is a combination of b,
a, c.

In VHDL it would be:

signal sel := std_logic_vector(2 downto 0);

begin

sel <= b & a & c;

with sel select y <=
a and b when "000",
c when "001",
a and b when "010",
'1' when "011",
a and b when "100",
'0' when "101",
a and b when "110",
a xor b when "111";

And now ask ChatGPT to translate this in Verilog:

Question:

Translate

signal sel := std_logic_vector(2 downto 0);

begin

sel <= b & a & c;

with sel select y <=
a and b when "000",
c when "001",
a and b when "010",
'1' when "011",
a and b when "100",
'0' when "101",
a and b when "110",
a xor b when "111";

to Verilog.

reg [2:0] sel;

always @* begin
case (sel)
3'b000, 3'b010, 3'b100, 3'b110: y = a & b;
3'b001: y = c;
3'b011: y = 1'b1;
3'b101: y = 1'b0;
3'b111: y = a ^ b;
endcase
end

assign sel = b & a & c;

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Mattia wrote:
> i need to write this circuit in verilog.
> Thanks.

Wow... nice to know!

So GO FOR IT!

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Gustl B. wrote:
...
> assign sel = b & a & c;

Ouch... obviously chatGPT needs to learn a bit more about the
differences between VHDL and Verilog.

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module mux(input b,a,c,
output reg y );
always@(b,a,c)
begin
if(!b)
assign y=c;
else if(b)
begin
assign y=a;
if(a==1 && c==1)
assign y=1'b0;
end
end
endmodule

this code was successfully executed on xilinx vivado

testbench

module tb;
reg b,a,c;
wire y;
mux uut(b,a,c,y);
initial
begin
b=1'b0; a=1'b0; c=1'b0;
#10 b=1'b0; a=1'b0; c=1'b1;
#10 b=1'b0; a=1'b1; c=1'b0;
#10 b=1'b0; a=1'b1; c=1'b1;
#10 b=1'b1; a=1'b0; c=1'b0;
#10 b=1'b1; a=1'b0; c=1'b1;
#10 b=1'b1; a=1'b1; c=1'b0;
#10 b=1'b1; a=1'b1; c=1'b1;

#20 \$finish;
end
endmodule

sorry if am too early😅