# Forum: FPGA, VHDL & Verilog Verilog circuit

Rate this post
 • ▲ useful ▼ not useful
i need to write this circuit in verilog.
Thanks.

Rate this post
 • ▲ useful ▼ not useful
Well ... how are a, b and c connected at the bottom of the MUX? The left
input is b, then a and right is c. So 000 ... 111 is a combination of b,
a, c.

In VHDL it would be:

signal sel := std_logic_vector(2 downto 0);

begin

sel <= b & a & c;

with sel select y <=
a and b when "000",
c when "001",
a and b when "010",
'1' when "011",
a and b when "100",
'0' when "101",
a and b when "110",
a xor b when "111";

And now ask ChatGPT to translate this in Verilog:

Question:

Translate

signal sel := std_logic_vector(2 downto 0);

begin

sel <= b & a & c;

with sel select y <=
a and b when "000",
c when "001",
a and b when "010",
'1' when "011",
a and b when "100",
'0' when "101",
a and b when "110",
a xor b when "111";

to Verilog.

reg [2:0] sel;

always @* begin
case (sel)
3'b000, 3'b010, 3'b100, 3'b110: y = a & b;
3'b001: y = c;
3'b011: y = 1'b1;
3'b101: y = 1'b0;
3'b111: y = a ^ b;
endcase
end

assign sel = b & a & c;

Rate this post
 • ▲ useful ▼ not useful
Mattia wrote:
> i need to write this circuit in verilog.
> Thanks.

Wow... nice to know!

So GO FOR IT!

Rate this post
 • ▲ useful ▼ not useful
Gustl B. wrote:
differences between VHDL and Verilog.