Hello, I would like to know if anyone needs a Low Frequency Multiplying Phase Locked Loop for their FPGA, CPLD designs with the following specs: 1. Instant lock 2. Small foot print 3. 2ns lock to leading edge 4. 10 bit multiplier value 5. Clock in frequency = don't care 6. Clock in frequency around 12MHz 7. Input sample frequency 10Hz to 1000Hz auto ranging 8. Stable 9. Jitter -2ns 10. Generates LOCKED and OVERFLOW If you could use this IP please let me know and how would you use it?
Hi Joseph, release on opencores.org or github and look what happends :) BR, Andreas
The 2ns jitter seem to be the result of a sampled edge with a self running clock at 500MHz, which is a typical clock frequency of such self running clocks. Well this is much to much for a typical FPGA app. Generally I wonder for which kind of apps this solution might by appropriate: Typically one will use any internal pll in an FPGA and use feedback loops to adjust to an incoming low frequent clock signal. This way one can adapt to signals of around 1/50 of the system pll clock, e.g. 20MHz internal and 500kHz external with less than 100ps. Also todays FPGA PLLs are tolerant downwards to 5MHz using non phase locked operation mode (DCM only), and 15MHz in phase locked operation mode. On the other hand clock frequencies below 10MHz are not appropriate for high speed designs since the incoming jitter is already too high. This is the reason why we use at least 100MHz RefClk for e.g. DDR RAM designs. If one uses around 1MHz input osc frequency for instance, one will have to accept at least 1ns jitter because of the mitigation ratio of 2:1 limiting the subsequent circuits jitter budget to 100MHz. Using a common PLL with an appropriately selected division ratio coming close to the input and using phase loop. So I do not see the reason for a complex digital PLL to derive internal system clock frequencies.
Well, you have a clock of 10MHz and can run the FPGA internally with 200MHz. Then I guess, you don't have this jitter.
My low frequency pll for use in VLSI devices uses a sysclk of 6 to 16MHz (tested). The leading edge of the pll input frequency is locked to the leading edge of the output frequency with a gate delay of two. For further specs see my patent #11290117 or contact me. I would be glad to discuss what my LFPLL can do.
mercatore wrote: > The 2ns jitter seem to be the result of a sampled edge with a self > running clock at 500MHz, which is a typical clock frequency of such self > running clocks. Well this is much to much for a typical FPGA app. > Generally I wonder for which kind of apps this solution might by > appropriate: > Typically one will use any internal pll in an FPGA and use feedback > loops to adjust to an incoming low frequent clock signal. This way one > can adapt to signals of around 1/50 of the system pll clock, e.g. 20MHz > internal and 500kHz external with less than 100ps. > Also todays FPGA PLLs are tolerant downwards to 5MHz using non phase > locked operation mode (DCM only), and 15MHz in phase locked operation > mode. > On the other hand clock frequencies below 10MHz are not appropriate for > high speed designs since the incoming jitter is already too high. This > is the reason why we use at least 100MHz RefClk for e.g. DDR RAM > designs. > If one uses around 1MHz input osc frequency for instance, one will have > to accept at least 1ns jitter because of the mitigation ratio of 2:1 > limiting the subsequent circuits jitter budget to 100MHz. Using a common > PLL with an appropriately selected division ratio coming close to the > input and using phase loop. > So I do not see the reason for a complex digital PLL to derive internal > system clock frequencies. My invention was developed for use on the design of a digital speed controller. I was interested in characterizing a motor driven by a pass-drive IGBT. My interest was graphing the power of the motor firing the IGBT at fixed angles. My invention works great in this application. I use a SYSCLK of 10 to 20MHz so my delta time is 50 ns which is undetectable when you are looking at low power frequencies i.e. 50/60Hz. The two gate delay jitter is the time between the leading edge of the input frequency and the leading edge of the output frequency. I'm aware that today's FPGA's Pll must operate at or above 5MHz. That is precisely why I developed my Low Frequency PLL. I'm not interested in High-frequency design for my application. I'm not the only VLSI designer that can use my design.
mercatore wrote: > The 2ns jitter seem to be the result of a sampled edge with a self > running clock at 500MHz, which is a typical clock frequency of such self > running clocks. Well this is much to much for a typical FPGA app. > Generally I wonder for which kind of apps this solution might by > appropriate: > Typically one will use any internal pll in an FPGA and use feedback > loops to adjust to an incoming low frequent clock signal. This way one > can adapt to signals of around 1/50 of the system pll clock, e.g. 20MHz > internal and 500kHz external with less than 100ps. > Also todays FPGA PLLs are tolerant downwards to 5MHz using non phase > locked operation mode (DCM only), and 15MHz in phase locked operation > mode. > On the other hand clock frequencies below 10MHz are not appropriate for > high speed designs since the incoming jitter is already too high. This > is the reason why we use at least 100MHz RefClk for e.g. DDR RAM > designs. > If one uses around 1MHz input osc frequency for instance, one will have > to accept at least 1ns jitter because of the mitigation ratio of 2:1 > limiting the subsequent circuits jitter budget to 100MHz. Using a common > PLL with an appropriately selected division ratio coming close to the > input and using phase loop. > So I do not see the reason for a complex digital PLL to derive internal > system clock frequencies. My invention was developed for use on the design of a digital speed controller. I was interested in characterizing a motor driven by a pass-drive IGBT. My interest was graphing the power of the motor firing the IGBT at fixed angles. My invention works great in this application. I use a SYSCLK of 10 to 20MHz so my delta time is 50 ns which is undetectable when you are looking at low power frequencies i.e. 50/60Hz. The two gate delay jitter is the time between the leading edge of the input frequency and the leading edge of the output frequency. I'm aware that today's FPGA's Pll must operate at or above 5MHz. That is precisely why I developed my Low Frequency PLL. I'm not interested in High-frequency design for my application. I'm not the only VLSI designer that can use my design. Torftroll wrote: > Well, you have a clock of 10MHz and can run the FPGA internally > with 200MHz. Then I guess, you don't have this jitter. My design is an arithmetic design. The operation is nothing like standard PLLs today. The result is similar to analog PLL's found on the shelf today. If you wish to understand my design, check out patent US 11,290,117 or contact me and I will explain my design. Andreas wrote: > Hi Joseph, > release on opencores.org or github and look what happends :) > BR, > Andreas Andreas, Thanks for the open source possibility ideal but my plans aren't headed in that direction. I'm using my design in a specialized motor controller and will enjoy the protection of the design that my patent affords me. Joe
Yes, I am interested. This may be helpful for generating trigger pulses off of the reference laser in an FT NIR spectrometer.
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