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Signal clock generator
von Filip (laugher)

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Hello everyone, I am new to VHDL so basically I need help with vhdl code 
that I have to do till friday for college.
I'm working in Xilinx ISE (dev sys is E2LP)

"Design a clock signal generator circuit. Using switches on the 
development system, the frequency of the clock signal should be able to 
be selected as: 3 Hz, 6 Hz, 12 Hz, 24 Hz, 100 Hz, 1000 Hz and 2000 Hz."

So I have been working on solution but I'm not sure if it is going to 
work on E2LP. Any help is going to be appreciated

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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entity clock_generator is

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    Port ( clk_sel : in STD_LOGIC_VECTOR(3 downto 0);

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           clk : out STD_LOGIC);

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end clock_generator;

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architecture Behavioral of clock_generator is

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    signal clk_int : std_logic := '0';

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    signal clk_freq : integer := 3;

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begin

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    clk_gen: process(clk_sel)

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    begin

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        case clk_sel is

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            when "0000" => clk_freq := 3;

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            when "0001" => clk_freq := 6;

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            when "0010" => clk_freq := 12;

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            when "0011" => clk_freq := 24;

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            when "0100" => clk_freq := 100;

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            when "0101" => clk_freq := 1000;

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            when "0110" => clk_freq := 2000;

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            when others => null;

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        end case;

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    end process;

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    clk <= not clk_int;

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    clk_int_gen: process(clk)

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    begin

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        clk_int <= not clk_int after (1000000/clk_freq) ns;

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    end process;

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end Behavioral;


  


  




  

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    Re: Signal clock generator
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Filip wrote:
> not sure if it is going to work on E2LP
Give it a try. Start the synthesizer and look what happens.

But to go into future: it won't work. Simply because inside the FPGA 
isn't anything like a "variable drlay" like that you want to get with 
"after (1000000/clk_freq) ns;"

In your FPGA you will have to use flip-flops and logic (in the LUTs) to 
create a counter that counts some clock-cycles and toggles a flag after 
reaching a desired prescaler value.

With other words: why reenventing the wheel? Simply look how others did 
the job and try to understand what they did.

  


  



  

  
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