I am trying to learn how to read from file in VHDL, the vhdl_code.vhd implements a low pass moving average filter, I already have a separate vhdl code Read_File.vhd that reads the data, now I have to read the column data from the file data2fpga.dat, and perform the low-pass operations in vhdl_code.vhd. My question is, should the Read_file.vhd should run as testbench or, how exactly i can perform this, i.e. how can I invoke the vhdl_code.vhd into Read_file.vhd? Any guidance will be highly appreciated. Thanks.
Re: How to instantiate another vhd file inside testbench, where the testbench is used for opening fi
Zahid wrote: > should the Read_file.vhd should run as testbench A testbench does not have any ports in its entity, because it is the uppermost level of the design. So it looks like the ReadFile may be a component of your testbench. And the testbench manages the interconnets between the ReadFile and lab111 components.
Re: How to instantiate another vhd file inside testbench, where the testbench is used for opening fi
@Von Lothar, I never coded a testbench which has a component that happens to be a testbench itself, this is the first time I am seeing it, the problem is the clk signal, both entity lab111 and ReadFile have clk ports, you are right, testbench should NOT have any ports, but I tried to perform the operations nevertheless, & I got the error "Declaration with designator "clk" already exists in this region." If it is not much to ask, I could not find any tutorials that have similar problems, can you guide me to any literature or learning videos so that I can learn & solve this problem? Thanks a lot for replying to the previous message. Zahid.
Re: How to instantiate another vhd file inside testbench, where the testbench is used for opening fi
In the testbench you define ak clock signal and in the very same test bench you connect that clock signal to all components needing that clock signal. Look how iI do it there with some components (its German, but Google translator will do it): - http://www.lothar-miller.de/s9y/archives/57-Sinusausgabe-mit-PWM.html Top level is the testbench which generates a clock signal. In the test bench the clock ist connected to the SinusPWM. And in the SinusPWM there are two components which also get that clock signal routed through. So all in VHDL designs there only are entities which act as components in other entities.
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Edited by Moderator
Re: How to instantiate another vhd file inside testbench, where the testbench is used for opening fi
Ok, thank you Mr. Lothar, your comment "So it looks like the ReadFile may be a component of your testbench." solved my issue. You are right, testbenches should not have entities, i created a new testbench, instantiated both the ReadFile and Lab111 as components, make the necessary port and generic maps & was finally able to load the data into the testbench. Thanks again. Best of Regards, Zahid.
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