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Forum: FPGA, VHDL & Verilog Concurrent VS Sequencial


von Mariana D. (vtrmg)


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Hey, I'm making a binary ordering. I have two questions: 1. Is there any 
way that I can make this code simpler? 2. Can I make this code 
concurrent or sequential using the functions I already write on top?

Thanks,
;D


------------------------------------------------------------------------ 
----------
package MY_PACKAGE is
   function portaand(SIGNAL A , B: in bit) return bit;
   function portaor(SIGNAL A , B: in bit) return bit;
END MY_PACKAGE;
---------------------------------------------------------------------
PACKAGE BODY MY_PACKAGE is
  FUNCTION portaand (SIGNAL A, B: bit )
  RETURN bit IS
  BEGIN
    RETURN A AND B;
  END portaand;

  FUNCTION portaor (SIGNAL A, B: bit )
  RETURN bit IS
  BEGIN
    RETURN A OR B;
  END portaor;

END MY_PACKAGE;
--------------------------------------------------------------------
use work.MY_PACKAGE.all;
--------------------------------------------------------------------

entity ORDENADORBINARIO is
  PORT ( n4, n3,n2,n1,n0 : IN bit;
       y4,y3,y2,y1,y0 : OUT bit );
end ORDENADORBINARIO;

architecture Behavioral of ORDENADORBINARIO is
  SIGNAL x0,x1,x2,x3,z0,z1,z2,w0,w1,w2,o0,o1,p0,p1,q0 : bit;
begin
  x0 <= portaand( n4 , n3 );
  z0 <= portaor( n4 , n3 );
  x1 <= portaand( n2 , z0 );
  z1 <= portaor( n2 , z0 );
  x2 <= portaand( n1 , z1 );
  z2 <= portaor( n1 , z1 );
  x3 <= portaand ( z2, n0);
  w0 <= portaand ( x0, x1) ;
  o0 <= portaor ( x0, x1) ;
  w1 <= portaand ( o0, x2) ;
  o1 <= portaor ( o0, x2) ;
  w2 <= portaand ( o1 , x3) ;
  p0 <= portaand (w0 , w1) ;
  q0 <= portaor( w0,w1);
  p1 <= portaand ( w2 , q0);




  y4 <= portaor (n0, z2);
  y3 <= portaor (o1, x3) ;
  y2 <= portaor ( w2, q0);
  y1 <= portaand (p0 , p1 );
  y0 <= portaor (p0 , p1);





end Behavioral;

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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there is no need for customized "or" and "and" funktions. In real life 
everybody would write it somehow this way:
1
entity ORDENADORBINARIO is
2
  PORT ( n4, n3,n2,n1,n0 : IN bit;
3
       y4,y3,y2,y1,y0 : OUT bit );
4
end ORDENADORBINARIO;
5
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architecture Behavioral of ORDENADORBINARIO is
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  SIGNAL x0,x1,x2,x3,z0,z1,z2,w0,w1,w2,o0,o1,p0,p1,q0 : bit;
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begin
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  x0 <= n4 and n3;
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  z0 <= n4 or n3;
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  x1 <= n2 and z0;
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  z1 <= n2 or z0;
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  :
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  : 
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  y4 <= n0 or z2;
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  y3 <= o1 or x3;
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  y2 <= w2 or q0;
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  y1 <= p0 and p1;
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  y0 <= p0 or p1;
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21
end Behavioral;

But much better redable would be to use vectors:
1
entity ORDENADORBINARIO is
2
  PORT ( n : IN  bit_vector (4 downto 0);
3
         y : OUT bit_vector (4 downto 0));
4
end ORDENADORBINARIO;
5
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architecture Behavioral of ORDENADORBINARIO is
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begin
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  y <= "01000" when n = "00000" else
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  y <= "01010" when n = "00001" else
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  y <= "01100" when n = "00010" else
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  y <= "01001" when n = "00011" else
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  y <= "01010" when n = "00100" else
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  :
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  :
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  y <= "11000" when n = "11100" else
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  y <= "01100" when n = "11101" else
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  y <= "01010" when n = "11110" else
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  y <= "01011";  -- n = "11111"
19
end Behavioral;
Litle hint: of course you must insert the correct values for those y <= 
"?????" assignments.

: Edited by Moderator
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