EmbDev.net

Forum: FPGA, VHDL & Verilog 8 bit full adder issue (i'm newbie in vhdl)


von Marco (pastaman71)


Attached files:

Rate this post
useful
not useful
i was following my teacher lecture  and i copied his code. His compiler 
didn't gave any warning or error, but when i try to compile it with my 
PC, it turns out some warning about non-bounded components. I tryied to 
use also std_logic instead of bit, but nothing (idk i tryied it all). 
I'm starting hating vhdl and i don't know what i have to do. Do you guys 
have any idea?
Thank you all in advance

: Edited by User
von Lothar M. (Company: Titel) (lkmiller) (Moderator)


Rate this post
useful
not useful
Marco wrote:
> and i copied his code.
Not all of it. The entity for component cfa is missing. Maybe its your 
job to write it.

> Do you guys have any idea?
Start on your own with a simple counter.

> I'm starting hating vhdl and i don't know what i have to do.
Wrong order.
But however, its simple to cure: learn it. And be sure: Verilog won't be 
any better.

: Edited by Moderator
von Marco (pastaman71)


Rate this post
useful
not useful
Lothar M. wrote:
> Not all of it. The entity for component cfa is missing. Maybe its your
> job to write it.

Thank you for the answer. May i ask some more? What i thought was that 
my entity "addern" was like a black box where inside the are 8 full 
adder that i declared with "component".
Are you telling me that i have to create an entity for the single full 
adder and from that use the component to make the 8-bit F-A?
Briefly, i have to make a F-A?
Thank you

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


Rate this post
useful
not useful
You need code for 1 component cfa because this missing component cfa is 
used n times in the adder_n entity.

Simply search for cfa in the posted code and do a little bit 
brainstorming on the search results.

von Marco (pastaman71)


Attached files:

Rate this post
useful
not useful
OMG i made the entity cfa ( literally the logical function of a full 
adder) and now it works !!! Thank you a lot my saviour!!

I also upload the code if someone need it some day.

SOLVED

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


Rate this post
useful
not useful
Marco wrote:
> now it works !!!
You see: VHDL isn't that horrible. For me its simply straight forward... 
;-)

> Thank you a lot
You're welcome.

Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.