Hi everyone,
I’m new to Verilog (and this forum) and currently learning through some problem sets: https://hdlbits.01xz.net/wiki/Problem_sets. I’m working on creating a data latch, data flip-flop and circuit with this elements using a structural approach, specifically without using any always blocks.
I successfully implemented a master-slave data flip-flop itself, and also passed the tests for synchronous and asynchronous reset tasks. However, I ran into issues with the following tasks:
https://hdlbits.01xz.net/wiki/Exams/m2014_q4d https://hdlbits.01xz.net/wiki/Mt2015_muxdff
In the first task, my output was always inverted. I suspected it might be due to incorrect initialization, so I did a quick fix by inverting the output, and that worked.
In the second task, there is one mismatch out of 199 cases: in the first half-cycle, the output is 1 instead of 0. I am wondering if this issue is also related to the initialization of my data flip-flop. I attempted to set the output to 0 using both an initial block and by declaring it as = 0 in the module declaration, but neither approach resolved the issue.
Since I don’t have control over the testing environment, I can't reset the data flip-flop at the start.
Also I would prefer NOT to use high-level always blocks.
Is there anything I can do to fix these problems?
I am attaching a file with the current incorrect (1 out of 199 mismatch) second problem solution
Thank you!