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Forum: FPGA, VHDL & Verilog modulo 100 VHDL


von Matlabo (matlabo)


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Hi !
 I am trying to implement a modulo 100 counter.

I encounter some issues with the Bin2BCD part.
The thing is that the incrementation of the tens digit is done two by 
two, like it goes from 0 to 2 then to 4 etc... and I don't understand 
why ?

Any help is deeply appreciated.

P.S: In the attachment I also added the code of the other parts in the 
Codes.rar file.

P.S2: I am running the simulation on ISE and it takes too much time. Any 
tips in order to reduce the simulation time ?

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Matlabo wrote:
> Any help is deeply appreciated.
Do you have a working test bench for that design?

I made one and it does not schow anything making any kind of sense to 
me...

Matlabo wrote:
> P.S2: I am running the simulation on ISE and it takes too much time. Any
> tips in order to reduce the simulation time ?
You must speed up your clock enables:
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architecture Behavioral of diviseur is
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:
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    elsif rising_edge (Clk) then 
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--      if qt=50000000 then 
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      if qt=4999 then 
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        enlh <='1' ;
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:
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--      if qt100 = 500000 then 
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      if qt100 = 49 then 
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        en100h <= '1';
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:
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  end process;
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end Behavioral;

> 50000000 ... 500000
The usual "off-by-one" problem: with a compare value of 500000 you count 
500001 clock cycles. Considering that it is very crude to handle the 
ones and hundreds by two separate prescalers:
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    elsif rising_edge (Clk) then 
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      if qt=50000000 then 
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        enlh <='1' ;
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        qt := 0;
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      else enlh <= '0' ;
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        qt := qt+1 ;
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      end if;
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      if qt100 = 500000 then 
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        en100h <= '1';
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        qt100 := 0;
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      else
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        qt100 := qt100 + 1;
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      end if;
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    end if;
Why don't you handle the digits in a way every "usual" counter does:
when the ones reach 9, then with the next clock the tens are 
incremented and the ones are reset to 0. When the tens reach 9 then 
with the next clock the hundreds are incremented and the tens are 
reset. And so on...

Have a look at the code of the stop watch there:
http://www.lothar-miller.de/s9y/archives/88-VHDL-vs.-Verilog-am-Beispiel-einer-Stoppuhr.html

Its German, try Google translator.

BTW:
1
use IEEE. numeric_STD.ALL;
2
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Never ever both of them together! The numeric_std has all you need.
With both of them you will now and then encounter weird error messages 
due to double definitions of some data types.

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