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Subject Author Replies Last post
PI loop filter in Verilog Rock B. 3
Artix-7 SPI (x4) bitstream does not work for SelectMAP (x16) St. D. 2
Generic Adder in VHDL Martin 7
DOGXL160-7 with MSP430G2452 through I2C toann 0
Smoke detector upcycling? Mike 6
VIVADO vs ISE elico 2
Deriving different clock signals from a system clock - frequency division & flags Sushma K S 2
LUT utilization is 121 % Lakshita J. 11
Synthesis doesn't match simulation Kyle Gacek 4
External oscillator on my LatticeXP2 Brevia2 Neoz 5
Phase detector in Xilinx Rock B. 23
USB Host CDC connection (to Surf Stick) on a frdmk64F (Cortex M4) Bastian S. 0
Digital Mixer implementation for DUC/DDC ATIF JAVED 2
Combinatorial logic Julian Mortimer 0
Filesystem for NOR flash Peter Ivanov 0
locked Want to join us? Can you develop a sleep-tracker like wearable? Alex Ander 0
Count number of more than 4 consecutive zeros Usman Ashraf 4
4-bit counter simulation problem Paolo 2
simple syntax error near clk Rock B. 11
QSPI - STM32F7 Petr Klaun 15
how to program mojo plus board with ise design Pouya Nosratkhah 1
Implement FIR filter in verilog using FDA tool Usman Ashraf 5
Help in simulating ALU with register file Fadi CPP 0
how to scale output of butterfly unit radix 2 for further stages Pravesh Rathee 2
VHDL code HELP PLZ CARL 1
RS232 from http://www.lothar-miller.de. SparkyT 1
I2C/TWI and FreeRTOS on Arduino Mega2560 / AVR Oliver G. 0
An array of std_logic_vector driven by two processes. Pablo Picasso 2
[QUESTION] Satnav firmware disassembly - help required :) RowanX 0
Quartus II connect bus to 2D array-input of block C17 3
SPI communication between two microcontrollers jeorges FrenchRivera 13
verbose output from quartus Quentin 0
Where is the Thermometer Project Thermometerbuilder 7
building a cross toolchain for 68k, avr and arm alexander 0
How to use the AVR Assembler (AVRASM2) for complex projects Thomas R. 7
the verilog code occupies the hole resources Alireza Shavakandi 3
VGA controller-Verilog sinhton 9
Zero-overhead blocking AXI4-stream function Julian Mortimer 0
Systolic Array Dayana Saiful 20
Is this nonesense? Julian Mortimer 3
Need help in code Gombo Khorloo 3
Help in vhdl project Bozidar Kelava 7
Display registers value - ARM assembly Ab Abrams 1
PSO based fir filter design and functional verification in fpga Bharat Lal106 3
Skipped part of design Op Op 2
Using a button for two functions play/pause Ya Yo 2
ATMEL-ICE Basic + AVR Studio 7 + ATMEGA8L-8PU Winfried Babinsky 1
Tocken bucket based on FIFO Melisa Čehajić 0
checking different channels Richard Turner 7
SNAKE GAME VHDL Ya Yo 4
Input Capture using FPGA Michael Javier 1