EmbDev.net

Forum: FPGA, VHDL & Verilog


Programmable logic


Subject Author Replies Last post
sticky FPGA development resources Andreas S. 15
Virtual Device in Vivado(Xilinx) Francy Akkara 0
Multiplexer Help john Wilson 11
Open Source Hardware Santosh Reddy Nallamada 1
question to generics and ports Andreas Felber 2
Flash memory soufiane 0
6-bit binary to BCD HELP Paulo Henrique Silva 3
Using ADC output in VHDL Francois Fmousse 2
Implementing an ADC Interface to connect to a FPGA Wilson 0
Arithmetic on fpga Abraziv Abraziv 5
Lattice EFB Simulation Martin La Torre 3
Sending binary data from Matlab to FPGA using the serial port Isamel 2
large project- understnd /decode large project- understnd /decode 3
AXI4 Streaming Interface Ragnarok BeDestroy 1
AMBA architecture Sai Kapp 1
RAMs and ROMs on FPGA Boards Ario Kian 2
Can't compile duplicate declarations of entity "xyz" into library "test" Hugo Hirsch 2
Vector with several components jackoup 1
No feasible entries for infix operator "=" VHDL New user 1
How to set the startup clock in PlanAhead? xilinx_newbee 1
Error Loading Design VHDL New user 2
Xilinx Spartan 3e no play Le Thang 1
[HELP] VHDL "cant infer register." Paulo Henrique Silva 2
2's Complement in verilog verilog code for two's complement 5
[HELPME] How to unstuck at VCC? Paulo Henrique Silva 5
Carry Look Ahead Adder showing U at last bit position in SUM Rohan Narkhede 3
Error: Coudl not Implement register on this clock edge Rex 1
changing outbit value david 8
How long it takes to develop a Verilog SPI core? Andy Vu 5
How to design register based logic core or IP? Andy Vu 0
boot NIOS and FPGA from EPCS flash jeorges FrenchRivera 5
Lattice iCE40-HX8K Board - UART Zumby 5
VGA pins compatibility for Spartan 3 and Altera DE2 (verilog) Charan Mehta 3
multiple schematicsheet connections Hugh Smith 1
fpga board selection Hamid Kavian Athar 2
Unexpected Synthesized bit order in Quartus with SystemVerilog Joshua Vasquez 3
Increasing dutycycle for an output signal Robert 14
Measuring/Reading Circuit Design Propagation Delay (in Quartus) Joshua Vasquez 4
Hello world VHDL Junior Hpc 8
Verilog Code LED if y = a & b !HELP! Verilog 1
locked How to interact with Lattice FPGA Banane 8
How to use UART on Lattice ICEStick Banane 3
SPI_slave testbench puka1012 3
recursive average calculation Timon 1
Keeping Hierarchy in post-layout simulation using Microsemi designer Ioannis Sideris 0
Scaling to a 12-bit ADC value Wil 7
SPI Master/Slave Interface Nayan Patel 10
Safe FSM design SparkyT 4
I am having difficulties with synthesis Manish Singh 6
Commercial FPGA security implementations post_ex0dus 3
Case statement choices cover only 4 out of 81 cases. puka1012 3
SPI slave open core simulation diagram puka1012 3