changing outbit value

david Guest #4280491
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hello,
I try to right a code that in every, say, clock change(not only a rise) 
it will change the out bit from 1 to 0 or from 0 to 1.

the architecture part is
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architecture arc_wat of wat is

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    signal a:std_logic:='1';

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begin

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  outb<=a;

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  process(clk)

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  begin

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    a<=not(a);

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  end process;

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end arc_wat;


I tried to declare a in  the proccess and to move the outb<=a; to the 
process as well-still doesnt work-> in the simulation outb is 
undefined...

I tried to simplify a bigger problem, and yet i can't see why it is'nt 
working.

anyone see where is my error?

thank you!!!
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Lothar M. Moderator (Company: Titel) #4280522
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david wrote:
> I tried to declare a in  the proccess and to move the outb<=a; to the
> process as well-still doesnt work-> in the simulation outb is
> undefined...
So the problem is NOT in the posted code...

1. Usually a VHDL description begins with "library ieee;". Thats missing 
here.
2. What toolchain do you use?
3. What is your testbench?
4. What do you expect and what do you get instead?

> in the simulation outb is undefined...
What does clk look like? Is it toggling?
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david Guest #4280534
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the hole code is

library ieee;
use ieee.std_logic_1164.all;

entity wat is
  port(
      clk      :  in std_logic;
      outb    :  out std_logic
    );
end wat;

architecture arc_wat of wat is
    signal a:std_logic:='1';
begin

  outb<=a;


  process(clk)
  begin
    a<=not(a);
  end process;


end arc_wat;


the simulation is attached.

i expect to see outb shifting from 1<->0
Attached files:
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david Guest #4280552
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1
library ieee;

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use ieee.std_logic_1164.all;

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entity wat is

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  port(

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      clk      :  in std_logic;

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      outb    :  out std_logic

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    );

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end wat;

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architecture arc_wat of wat is

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    signal a:std_logic:='1';

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begin

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  outb<=a;

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  process(clk)

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  begin

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    a<=not(a);

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  end process;

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end arc_wat;
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Lothar M. Moderator (Company: Titel) #4280655
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For me its simulating (some kind of) "well" in the behavioural 
simualtion...

But you have a VERY big mistake in your code!
> process(clk)
>   begin
>     a<=not(a);
>   end process;
The sensitivity list is WRONG, because the process is NOT dependent on 
the clk. Its only dependent on any change of a.
You must get one thing very clear: the sensitivity list is ONLY for the 
simulator. It ist not used by the synthesizer, its simply ignored by 
the synthesizer!

And therefore the process MUST be this way:
> process(a)
>   begin
>     a<=not(a);
>   end process;
And then you can see: theres absolutely no clk involved in the 
description!


OK, lets go one step backwards...
david wrote:
> I try to right a code that in every, say, clock change(not only a rise)
> it will change the out bit from 1 to 0 or from 0 to 1.
Because VHDL is a hardware description language you must have a 
"picture" or a sketch or something in front of you (or in your mind) you 
can describe.
What piece of hardware can react on either clock edge? Is there a kind 
of "double clock flipflop" inside your FPGA/CPLD?
No? Then you cannot use a description of such a piece of hardware in 
your code.

So again one step back: what do you want to do?
Attached files:
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david Guest #4280686
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I pulled this code out as a test to some part of my project that does 
not function properly.

I just wanted to simulate this code properly to test another thing,(i 
could have added (if rising_edge(clk)) but it is not the real point for 
me.

the simulation you uploaded was recieved from running my code with no 
changes?

what at my computer/quartus2 options could have caused me to recieve the 
simulation i uploaded?
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Lothar M. Moderator (Company: Titel) #4280731
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david wrote:
> the simulation you uploaded was recieved from running my code with no
> changes?
Yes, indeed. The "test bench" is attached here. I used Xilinx ISE ISIM 
for simulation.

Keep in mind: I ran a pre synthesis behavioural simulation. Maybe a 
post synthesis timing simulation will get your result...
Attached files:
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