changing outbit value

david Guest #4280491
Rate this post
• ▲ useful
▼ not useful 
hello,
I try to right a code that in every, say, clock change(not only a rise) 
it will change the out bit from 1 to 0 or from 0 to 1.

the architecture part is
1
architecture arc_wat of wat is

2
    signal a:std_logic:='1';

3
begin

4
  

5
  outb<=a;

6
  

7
  

8
  process(clk)

9
  begin

10
    a<=not(a);

11
  end process;

12


13
  

14
end arc_wat;


I tried to declare a in  the proccess and to move the outb<=a; to the 
process as well-still doesnt work-> in the simulation outb is 
undefined...

I tried to simplify a bigger problem, and yet i can't see why it is'nt 
working.

anyone see where is my error?

thank you!!!
Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
Lothar M. Moderator (Company: Titel) #4280522
Rate this post
• ▲ useful
▼ not useful 
david wrote:
> I tried to declare a in  the proccess and to move the outb<=a; to the
> process as well-still doesnt work-> in the simulation outb is
> undefined...
So the problem is NOT in the posted code...

1. Usually a VHDL description begins with "library ieee;". Thats missing 
here.
2. What toolchain do you use?
3. What is your testbench?
4. What do you expect and what do you get instead?

> in the simulation outb is undefined...
What does clk look like? Is it toggling?
Reply Quote Edit Delete Report post
david Guest #4280534
Rate this post
• ▲ useful
▼ not useful 
the hole code is

library ieee;
use ieee.std_logic_1164.all;

entity wat is
  port(
      clk      :  in std_logic;
      outb    :  out std_logic
    );
end wat;

architecture arc_wat of wat is
    signal a:std_logic:='1';
begin

  outb<=a;


  process(clk)
  begin
    a<=not(a);
  end process;


end arc_wat;


the simulation is attached.

i expect to see outb shifting from 1<->0
Attached files:
Reply Quote Edit Delete Report post
david Guest #4280552
Rate this post
• ▲ useful
▼ not useful 
1
library ieee;

2
use ieee.std_logic_1164.all;

3


4
entity wat is

5
  port(

6
      clk      :  in std_logic;

7
      outb    :  out std_logic

8
    );

9
end wat;

10


11
architecture arc_wat of wat is

12
    signal a:std_logic:='1';

13
begin

14


15
  outb<=a;

16


17


18
  process(clk)

19
  begin

20
    a<=not(a);

21
  end process;

22


23


24
end arc_wat;
Reply Quote Edit Delete Report post
Lothar M. Moderator (Company: Titel) #4280655
Rate this post
• ▲ useful
▼ not useful 
For me its simulating (some kind of) "well" in the behavioural 
simualtion...

But you have a VERY big mistake in your code!
> process(clk)
>   begin
>     a<=not(a);
>   end process;
The sensitivity list is WRONG, because the process is NOT dependent on 
the clk. Its only dependent on any change of a.
You must get one thing very clear: the sensitivity list is ONLY for the 
simulator. It ist not used by the synthesizer, its simply ignored by 
the synthesizer!

And therefore the process MUST be this way:
> process(a)
>   begin
>     a<=not(a);
>   end process;
And then you can see: theres absolutely no clk involved in the 
description!


OK, lets go one step backwards...
david wrote:
> I try to right a code that in every, say, clock change(not only a rise)
> it will change the out bit from 1 to 0 or from 0 to 1.
Because VHDL is a hardware description language you must have a 
"picture" or a sketch or something in front of you (or in your mind) you 
can describe.
What piece of hardware can react on either clock edge? Is there a kind 
of "double clock flipflop" inside your FPGA/CPLD?
No? Then you cannot use a description of such a piece of hardware in 
your code.

So again one step back: what do you want to do?
Attached files:
Reply Quote Edit Delete Report post
david Guest #4280686
Rate this post
• ▲ useful
▼ not useful 
I pulled this code out as a test to some part of my project that does 
not function properly.

I just wanted to simulate this code properly to test another thing,(i 
could have added (if rising_edge(clk)) but it is not the real point for 
me.

the simulation you uploaded was recieved from running my code with no 
changes?

what at my computer/quartus2 options could have caused me to recieve the 
simulation i uploaded?
Reply Quote Edit Delete Report post
Lothar M. Moderator (Company: Titel) #4280731
Rate this post
• ▲ useful
▼ not useful 
david wrote:
> the simulation you uploaded was recieved from running my code with no
> changes?
Yes, indeed. The "test bench" is attached here. I used Xilinx ISE ISIM 
for simulation.

Keep in mind: I ran a pre synthesis behavioural simulation. Maybe a 
post synthesis timing simulation will get your result...
Attached files:
Reply Quote Edit Delete Report post
Watch this topic

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.