Hello, I have the following verilog code for my Lattice iCE40-HX8K Board: uart.v: module uart(input clk, output TXD); reg [3:0] count; reg [9:0] data; reg z; initial begin data[9:0] = 10'b1000000000; // Startbit = 1, Stopbit = 0 z = 0; end always@(posedge clk) begin if(count == 1250) //9600x per Second (1250) = Baudrate begin count <= 0; TXD = data[z]; z = z + 1; if(z == 10) begin z = 0; end else begin end end else begin count <= count + 1; end end endmodule For receiving the UART-Data I use gtkterm under Ubuntu 14.04. I have set the baudrate in gtkterm to 9600. If I now program my FPGA with the code I receive once per programming a hex "00" (irrespective of the 8 usage-bits). Can anybody give me a hint what is wrong? Thank you for your support. Sincerely, Zumby
I've know fixed two problems: 1. count has to be at least 11 Bits wide to count to 1250 2. z has to be at least 4 Bits wide to count to 10 3. Removed non-blocking assignments (<=) The code know looks like this: module uart(input clk, output TXD); reg [10:0] count; reg [9:0] data; reg [3:0] z; initial begin data[9:0] = 10'b0010100101; // Startbit = 0, Stopbit = 1 z = 0; end always@(posedge clk) begin if(count == 1250) //9600x pro Sekunde (1250) = Baudrate begin count = 0; TXD = data[z]; z = z + 1; if(z == 10) begin z = 0; end else begin end end else begin count = count + 1; end end endmodule I am now receiving an endless chain of "J" (like in the attachment). But if I take a look at the data bits inside "data": 01010010 I should receive a ASCII "R". My question is now why I am getting a "J" instead of an "R"? Can anybody give me a hint what might be wrong? Thank you a lot :) Sincerely, Zumby
The solution solves in 10 seconds if you have FAR commander installed: 1) create new file, readme.txt 2) type RJ i that file 3) close file 4) press F3 and F4, to get HEX view 52 4A you may have to write it down in binary to see the that the LSB-MSB bit order is wrong, reversed 0101 0010 Letter R after bit reversal 0100 1010 Letter J stay DIPSY.COOL you are on right learning path..
Zumby wrote: > if(count == 1250) //9600x pro Sekunde (1250) = Baudrate > begin > count = 0; With this your baudrate has the "usual" deviation of 1 clock: Your count counts from 0 to 1250, what are 1251 steps. To count 1250 steps you must count from 0 to 1249. You may say I'm splitting hairs, but thats a systematically problem. Maybe tomorrow you want to design a counter for 5 clock cycles. And then the deviation of 20% is significant...
Zumby wrote: > > 3. Removed non-blocking assignments (<=) > This is a bad idee. General guidelines are: Use blocking assignments in always blocks that are written to generate combinational logic. Use nonblocking assignments in always blocks that are written to generate sequential logic. For a discussion why see for example: http://www.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media=synth-verilog-cummins.pdf
I'd recommend you use constants that have the same amount of bits as the registers/wire that you are assigning to:
counter <= counter + 11'd1;
z <= z + 4'd1;
if (z == 4'd10)
@Lothar Miller: systematically is an adverb, you have to use an adjective to modify a noun (problem).