Hi everyone,
I was under the impression that the bit-order of values in SystemVerilog
was left-to-right: MSbit-to-LSbit.
Recently, I wrote up a 11-bit-wide multiplexer:
1 | module test_mux( input logic [10:0] input_a,
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2 | input logic override,
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3 | output logic [10:0] output_c);
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4 |
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5 | parameter [10:0] constant = 11'h00F;
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6 |
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7 | assign output_c = (override) ?
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8 | constant :
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9 | input_a;
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10 | endmodule
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expecting the more-significant bits to be zeros and the last four
less-significant bits to be ones. When I synthesized it and visualized
the result, though, I got the unexpected constant 11'h780 as my constant
input.
I tried an alternative:
1 | parameter [10:0] constant = 11'h00F;
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2 | always_comb
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3 | begin
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4 | integer i;
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5 | for (i = 0; i < 11; i = i + 1)
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6 | begin
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7 | output_c[i] = (override) ?
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8 | constant[i] :
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9 | input_a[i];
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10 | end
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11 | end
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and got the expected constant input to be 11'hf.
(a) Are the two above code snippets not the same??
(b) What is the expected bit-order in Quartus?
I'm ruling out that the RTL viewer is just rendering the values
incorrectly. To do so, for the unexpected result, I expanded the mux
input and saw that mux[0]: 1, mux[1]: 1 ... mux[10]:0, which would rule
out that Quartus' RTL viewer is just rendering the result incorrectly.
Thanks for taking a look, and I'd appreciate any leads on this!
Cheers!