Forum: FPGA, VHDL & Verilog Unexpected Synthesized bit order in Quartus with SystemVerilog

von Joshua V. (Company: Harvey Mudd College) (poofjunior)

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Hi everyone,

I was under the impression that the bit-order of values in SystemVerilog 
was left-to-right: MSbit-to-LSbit.

Recently, I wrote up a 11-bit-wide multiplexer:
module test_mux( input logic [10:0] input_a,
                 input logic  override,
               output logic [10:0] output_c);

parameter [10:0] constant = 11'h00F;                                            

    assign output_c = (override) ?
                        constant :

expecting the more-significant bits to be zeros and the last four 
less-significant bits to be ones. When I synthesized it and visualized 
the result, though, I got the unexpected constant 11'h780 as my constant 

I tried an alternative:
parameter [10:0] constant = 11'h00F;
    integer i;
    for (i = 0; i < 11; i = i + 1)       
    output_c[i] = (override) ?
                       constant[i] :

and got the expected constant input to be 11'hf.

(a) Are the two above code snippets not the same??
(b) What is the expected bit-order in Quartus?

I'm ruling out that the RTL viewer is just rendering the values 
incorrectly. To do so, for the unexpected result, I expanded the mux 
input and saw that mux[0]: 1, mux[1]: 1 ... mux[10]:0, which would rule 
out that Quartus' RTL viewer is just rendering the result incorrectly.

Thanks for taking a look, and I'd appreciate any leads on this!


: Edited by User
von Lattice User (Guest)

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It looks like a bug in Quartus, but this may be only in rendering the 
RTL view. Does Quartus also have a technology view?

(I have testet it with Synplify Pro (Lattice) and it worksn as 

von Joshua V. (Company: Harvey Mudd College) (poofjunior)

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Quartus does have a technology view, but from the looks of it I think 
the constant input is embedded in the logic cell without giving me any 
hints as to what value it's storing.

Thanks for the tip! I'll see if the folks at Altera have some more tips. 
(I'm using Quartus 15.0 right now.)

von Lattice User (Guest)

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There is an hint.
If you look closely, bits 0-3 are using the input DATAB on the logic 
cell, the others are using DATAD. So my guess it is a bug in the RTL 

Wrong synthesis result would be a killer bug.


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