I am using Libero 11.5 SP3, including Synplify Pro.
I need some help on how to synthesize safe FSMs.
In synplify, in the VHDL Compiler options, there is a High reliability
where i can tick 'Preserve and decode Unreachable States'. Once this is
ticked, I can see the RTL/Technology view with a state-error-detect box.
But once i flash the design, it fails. (I have a memory check test to
see this). This tick, applies to the whole design, more than 10 FSM's,
Once un-ticked, the design passes the memory test.
So i started looking into attibutes. So far I used the
attribute syn_safe_case : boolean; -- enables/disables the safe case option
attribute syn_safe_case of RTL : architecture is true; -- turns off sequential optimizations for counters, FSM, and sequential logic
attribute syn_encoding : string; -- Overrides the default FSM Compiler encoding for a state machine and applies the specified encoding
attribute syn_encoding of curr_st : signal is "safe"; -- default encoding and adds reset logic
either together or on their own, they all pass the memory test. I
definetely see different logic being synthesized, but cant see the
state-error-detect box, anywhere.
How can I know for sure that i synthesized a safe FSM?
How do you synthesize yours?
Thank you in advance