Hi all! i am new to VHDL and i was ask to write a program in VHDL to
implement a 3-input sequential Poller. The Poller has three inputs
representing three devices. A device request service by asserting its
input. On every clock cycle, the polling machine checks the status of
the three input devices and generates an output code that identifies the
asserted input(device) to be serviced, the device with the highest
priority is selected. Each input is assigned a fixed priority denoted by
its subscript; 3 is the highest priority and 1 is the lowest priority.
To prevent "starving" the lower devices, the same asserted input is
never selected on two successive pollings unless there are no other
asserted pins.
Poller.png
------------------------------------------------------------------------
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1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 |
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4 | entity poller is port
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5 | (
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6 | req : in std_logic_vector(3 downto 1):="000";
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7 | clk,nreset : in std_logic_vector;
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8 | ack : out std_logic_vector(1 downto 0)
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9 | );
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10 |
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11 | end poller;
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12 |
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13 | architecture behave of poller is
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14 |
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15 | type states is (none,req1,req2,req3);
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16 | signal state : states;
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17 |
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18 | begin
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19 |
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20 | moore : process(clk, nreset)
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21 | begin
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22 |
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23 | if(nreset = '1') then
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24 | state <=none;
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25 |
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26 | elsif(clk' event and clk = '1')then
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27 |
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28 | case state is
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29 | when none =>
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30 | if req(3)= '1' then
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31 | state <= req3;
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32 | elsif req(2)='1' then
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33 | state <= req2;
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34 | elsif req(1)='1' then
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35 | state <= req1;
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36 | end if;
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37 |
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38 | when req1 =>
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39 | if req(3)= '1' then
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40 | state <= req3;
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41 | elsif req(2)='1' then
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42 | state <= req2;
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43 | elsif req(1)='1' then
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44 | state <= req1;
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45 | else
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46 | state <= none;
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47 | end if;
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48 |
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49 | when req2 =>
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50 | if req(3)='1' and req(2)='0' and req(1)='0' then
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51 | state <= req3;
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52 | elsif req(3)='1' and req(2)='1' and req(1)='0' then
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53 | state <= req3;
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54 | elsif req(3)='1' and req(2)='0' and req(1)='1' then
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55 | state <= req3;
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56 | elsif req(3)='0' and req(2)='1' and req(1)='0' then
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57 | state <= req2;
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58 | elsif req(3)='0' and req(2)='0' and req(1)='1' then
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59 | state <= req1;
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60 | else
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61 | state <= none;
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62 | end if;
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63 |
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64 | when req3 =>
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65 | if req(3)='1' and req(2)='0' and req(1)='0' then
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66 | state <= req3;
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67 | elsif req(3)='1' and req(2)='1' and req(1)='0' then
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68 | state <= req2;
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69 | elsif req(3)='1' and req(2)='0' and req(1)='1' then
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70 | state <= req1;
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71 | elsif req(3)='0' and req(2)='1' and req(1)='0' then
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72 | state <= req2;
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73 | elsif req(3)='0' and req(2)='1' and req(1)='1' then
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74 | state <= req2;
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75 | elsif req(3)='0' and req(2)='0' and req(1)='1' then
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76 | state <= req1;
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77 | else
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78 | state <= none;
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79 | end if;
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80 |
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81 | end case;
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82 | end if;
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83 | end process;
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84 |
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85 | ack <= "00" when (state= none)
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86 | else "01" when (state= req1)
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87 | else "10" when (state= req2)
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88 | else "11";
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89 |
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90 | end behave;
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While compiling the code in Modelsim PE Student I get the following
error
** Error: C:/Users/work/h/vhdl/poller.vhd(24): No feasible entries
for infix operator "=".
** Error: C:/Users/work/h/vhdl/poller.vhd(24): **Type error
resolving infix expression "=" as type std.STANDARD.BOOLEAN.**
** Error: C:/Users/work/h/vhdl/poller.vhd(27): No feasible entries
for infix operator "=".
** Error: C:/Users/work/h/vhdl/poller.vhd(27): Bad expression in
right operand of infix expression "and".
** Error: C:/Users/work/h/vhdl/poller.vhd(27): Type error resolving
infix expression "and" as type std.STANDARD.BOOLEAN.
** Error: C:/Users/work/h/vhdl/poller.vhd(91): VHDL Compiler exiting
Any help is appreicated:)