EmbDev.net

Forum: FPGA, VHDL & Verilog No feasible entries for infix operator "="


von VHDL N. (darylczj1995)


Rate this post
0 useful
not useful
Hi all! i am new to VHDL and i was ask to write a program in VHDL to 
implement a 3-input sequential Poller. The Poller has three inputs 
representing three devices. A device request service by asserting its 
input. On every clock cycle, the polling machine checks the status of 
the three input devices and generates an output code that identifies the 
asserted input(device) to be serviced, the device with the highest 
priority is selected. Each input is assigned a fixed priority denoted by 
its subscript; 3 is the highest priority and 1 is the lowest priority. 
To prevent "starving" the lower devices, the same asserted input is 
never selected on two successive pollings unless there are no other 
asserted pins.
Poller.png

------------------------------------------------------------------------ 
--------
1
    library ieee;
2
    use ieee.std_logic_1164.all;
3
    
4
    entity poller is port
5
    ( 
6
      req        : in std_logic_vector(3 downto 1):="000";
7
      clk,nreset : in std_logic_vector;
8
      ack        : out std_logic_vector(1 downto 0)
9
      );
10
    
11
    end poller;
12
    
13
    architecture behave of poller is
14
      
15
    type states is (none,req1,req2,req3);
16
      signal state : states;
17
    
18
    begin
19
     
20
     moore : process(clk, nreset)
21
     begin
22
       
23
      if(nreset = '1') then
24
       state <=none;
25
       
26
      elsif(clk' event and clk = '1')then
27
     
28
     case state is
29
     when none =>
30
                  if req(3)= '1' then
31
                    state <= req3;
32
                  elsif req(2)='1' then
33
                    state <= req2;
34
                  elsif req(1)='1' then
35
                    state <= req1;
36
                  end if;
37
                  
38
      when req1 =>
39
                  if req(3)= '1' then
40
                    state <= req3;
41
                  elsif req(2)='1' then
42
                    state <= req2;
43
                  elsif req(1)='1' then
44
                    state <= req1;
45
                  else
46
                    state <= none;
47
                  end if;
48
        
49
      when req2 =>
50
                  if req(3)='1' and req(2)='0' and req(1)='0' then
51
                    state <= req3;
52
                  elsif req(3)='1' and req(2)='1' and req(1)='0' then
53
                    state <= req3;
54
                  elsif req(3)='1' and req(2)='0' and req(1)='1' then
55
                    state <= req3;
56
                  elsif req(3)='0' and req(2)='1' and req(1)='0' then 
57
                    state <= req2;
58
                  elsif req(3)='0' and req(2)='0' and req(1)='1' then
59
                    state <= req1;
60
                  else
61
                    state <= none;
62
                  end if;
63
        
64
      when req3 =>
65
                  if req(3)='1' and req(2)='0' and req(1)='0' then
66
                    state <= req3;
67
                  elsif req(3)='1' and req(2)='1' and req(1)='0' then
68
                    state <= req2;
69
                  elsif req(3)='1' and req(2)='0' and req(1)='1' then
70
                    state <= req1;
71
                  elsif req(3)='0' and req(2)='1' and req(1)='0' then 
72
                    state <= req2;
73
                  elsif req(3)='0' and req(2)='1' and req(1)='1' then 
74
                    state <= req2;
75
                  elsif req(3)='0' and req(2)='0' and req(1)='1' then
76
                    state <= req1;
77
                  else
78
                    state <= none;
79
                  end if;
80
                  
81
                end case;
82
              end if;
83
            end process;
84
            
85
      ack <= "00" when (state= none) 
86
    else "01" when (state= req1)
87
    else "10" when (state= req2)
88
    else "11";
89
      
90
    end behave;

While compiling the code in Modelsim PE Student I get the following 
error

    ** Error: C:/Users/work/h/vhdl/poller.vhd(24): No feasible entries 
for infix operator "=".
    ** Error: C:/Users/work/h/vhdl/poller.vhd(24): **Type error 
resolving infix expression "=" as type std.STANDARD.BOOLEAN.**
    ** Error: C:/Users/work/h/vhdl/poller.vhd(27): No feasible entries 
for infix operator "=".
    ** Error: C:/Users/work/h/vhdl/poller.vhd(27): Bad expression in 
right operand of infix expression "and".
    ** Error: C:/Users/work/h/vhdl/poller.vhd(27): Type error resolving 
infix expression "and" as type std.STANDARD.BOOLEAN.
    ** Error: C:/Users/work/h/vhdl/poller.vhd(91): VHDL Compiler exiting


Any help is appreicated:)

: Edited by Moderator
von VHDL N. (darylczj1995)


Rate this post
0 useful
not useful
i found a solution to it
instead of
1
library ieee;
2
use ieee.std_logic_1164.all;
3
4
entity poller is port
5
( 
6
  req        : in std_logic_vector(3 downto 1):="000";
7
  clk,nreset : in std_logic_vector;
8
  ack        : out std_logic_vector(1 downto 0)
9
  );
10
11
end poller;

it is
1
library ieee;
2
use ieee.std_logic_1164.all;
3
4
entity poller is port
5
( 
6
  req        : in std_logic_vector(3 downto 1):="000";
7
  clk,nreset : in std_logic;
8
  ack        : out std_logic_vector(1 downto 0)
9
  );
10
11
end poller;

i made a mistake at my entity.

: Edited by Moderator

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.