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Forum: FPGA, VHDL & Verilog How long it takes to develop a Verilog SPI core?


von Andy V. (Company: Self) (newembuser)


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Assuming you need to develop a SPI core in Verilog and implement it in 
FPGA.  How long would it take assuming only one person work.

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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What level of experience?
Beginner?
Expert?

For me it would eat about 40 hours with debugging and documentation in 
VHDL, because I know that very well.
It would need about 100 hours in Verilog, because I know VHDL very well.
It may need much much more for someone not knowing FPGA and any HDL...

: Edited by Moderator
von jemand (Guest)


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It also depends on the requirements on the core. Should it be flexible, 
parameterizable or should it just send e.g. fixed 2 bytes and read back 
a fixed length answer... The second option without andy documentation 
and only coarse testign should take less than 2 hours for a experienced 
user. The first option may take 1-2 weeks even for an experienced user 
as Lothar explains correctly.

von Andy V. (Company: Self) (newembuser)


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Thanks for the response.  By the way, does anyone here know a link to 
where I can get the SPI standard?

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Andy V. wrote:
> where I can get the SPI standard?
SPI is defined by Motorola. Its not a really "standard" but only two 
coupled shift registers. And therefore every SPI device has its own 
specific transmission parameters. The only way is to understand what SPI 
is really and implement a timing that suits the corresponding slave.
Have a look at that picture to see what SPI actually is:
http://www.lothar-miller.de/s9y/archives/15-SPI.html
(try Google translate, its German)

: Edited by Moderator
von Dussel (Guest)


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You can also look it up on Wikipedia (note: It is Serial Peripheral 
Interface and not SCSI Parallel Interface) or read in a datasheet. In 
contrast to I2C or other busses SPI it is very simple.

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