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Forum: FPGA, VHDL & Verilog Hello world VHDL

von Junior H. (Company: University) (junior_hpc)

2015-07-30 11:56

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Hello. I'm doing some test with Vivado. I imported the following VHDL 
code:

entity hello_world is
architecture hello_world of hello_world is
  stimulus : PROCESS
    assert false report "Hello World"
    severity note;
    wait;
  end PROCESS stimulus;
end hello_world;


The code seems correct but I get design error empty. Any idea?

Thanks

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Re: Hello world VHDL

von P. K. (pek)

2015-07-30 12:33

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You will be able to simulate this entity (the Simulator issuing "Hello 
World").
But as there are no outputs on the entity, the synthesis result will be 
empty (there is nothing required to produce nothing).

2015-07-30 12:33: Edited by User

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Re: Hello world VHDL

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2015-07-30 12:39

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Junior H. wrote:
> I get design error empty. Any idea?
What did you do?
What did you expect?
Why did you expect that?
Waht did you get instead?

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Re: Hello world VHDL

von Julio (Guest)

2015-09-02 21:56

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Moderator,
Junnior H expect a more friendly response .... no more questions to your 
question ..... If anyone
friendlier and who knows the subject ... please answer

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Re: Hello world VHDL

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2015-09-02 22:04

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Julio wrote:
> Junnior H expect a more friendly response ....
Maybe and obviously. And now?

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Re: Hello world VHDL

von r_u_d_i (Guest)

2015-09-02 22:50

Attached files:

VivadoHelloWorldTutorial.pdf (4.55 MB) | view

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Howdy Junior, u are welcome -

Junior H. wrote:
> Hello. I'm doing some test with Vivado. I imported the following VHDL
> code:
>

entity hello_world is                         -- test bench ok
architecture hello_world of hello_world is    -- declarations place ok
                                              -- [q] where are there ?
 begin                                        -- code place ok
   stimulus : PROCESS                         -- process ok
     assert false report "Hello World"        -- ?
     severity note;
     wait;
   end PROCESS stimulus;
 end hello_world;




> The code seems correct but I get design error empty. Any idea?

where you want 'report' your "Hello World" ?
and is this ok, only if process goes false?
you will never get a message if process was successfull ;-)


  assertion_statement ::= [ label : ] assertion ;


  assertion ::=
  ASSERT condition
    [ REPORT expression ]
    [ SEVERITY expression ];





have a look to a shool example :

-- hello_world.vhdl  Just output to the screen
--                   This should be independent of whose VHDL you use
--                   When using some vendors GUI, you have a learning curve
--                   Using portable VHDL, it will run on all vendors
--                   with implementations conforming to IEEE Std. 1076-1993
entity hello_world is  -- test bench (top level like "main")
end entity hello_world;
library STD;                            -- you don't need STD, it is automatic
library IEEE;                           -- but may need other libraries
use IEEE.std_logic_1164.all;            -- basic logic types
use STD.textio.all;                     -- basic I/O
use IEEE.std_logic_textio.all;          -- I/O for logic types
architecture test of hello_world is -- where declarations are placed
  subtype word_32 is std_logic_vector(31 downto 0);  -- simple name
  signal four_32 : word_32 := x"00000004";           -- just four in hex
  signal counter : integer := 1;                     -- initialized counter
begin  -- where parallel code is placed
  my_print : process is                  -- a process is parallel
               variable my_line : line;  -- type 'line' comes from textio
             begin
               write(my_line, string'("Hello World"));   -- formatting
               writeline(output, my_line);               -- write to "output"
               write(my_line, string'("four_32 = "));    -- formatting 
               hwrite(my_line, four_32); -- format type std_logic_vector as hex
               write(my_line, string'("  counter= "));
               write(my_line, counter);  -- format 'counter' as integer
               write(my_line, string'(" at time "));
               write(my_line, now);                     -- format time
               writeline(output, my_line);              -- write to display
               wait;
             end process my_print;
end architecture test;
-- compile/analyze this file, then simulate
-- the output on the screen should contain the following lines (without "-- ")
-- Hello World
-- four_32 = 00000004  counter= 1 at time 0 NS


attached is a Vivado Hello World example

best wishes
rudi ;-)

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Re: Hello world VHDL

von r_u_d_i (Guest)

2015-09-02 23:01

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push#

perhabs you can have a look to a simply hello world, like this:

use std.textio.all;
entity hello_world is
end hello_world;
architecture behaviour of hello_world is
write (output, String'("Hello world!"));
end process;
end behaviour;

;-)

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Re: Hello world VHDL

von r_u_d_i (Guest)

2015-09-03 03:21

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push#

https://forums.xilinx.com/t5/7-Series-FPGAs/Hello-World-vhdl/m-p/641855

have you solved your last?
are you generating with some jave tool again?

..

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Re: Hello world VHDL

von r_u_d_i (Guest)

2015-09-03 03:26

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push#
perhabs same issue like the cross post?
https://forums.xilinx.com/t5/Implementation/Place-30-494-The-design-is-empty/m-p/645476#M13148

bye
..

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