Hello world VHDL

Junior H. OP (Company: University) #4216501
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Hello. I'm doing some test with Vivado. I imported the following VHDL 
code:

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entity hello_world is

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end;

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architecture hello_world of hello_world is

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begin

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  stimulus : PROCESS

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  begin

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    assert false report "Hello World"

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    severity note;

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    wait;

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  end PROCESS stimulus;

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end hello_world;


The code seems correct but I get design error empty. Any idea?

Thanks
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r_u_d_i Guest #4257098
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Howdy Junior, u are welcome -

Junior H. wrote:
> Hello. I'm doing some test with Vivado. I imported the following VHDL
> code:
>
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entity hello_world is                         -- test bench ok

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end;

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architecture hello_world of hello_world is    -- declarations place ok

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                                              -- [q] where are there ?

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 begin                                        -- code place ok

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   stimulus : PROCESS                         -- process ok

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   begin                                      --

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     assert false report "Hello World"        -- ?

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     severity note;

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     wait;

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   end PROCESS stimulus;

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 end hello_world;




> The code seems correct but I get design error empty. Any idea?

where you want 'report' your "Hello World" ?
and is this ok, only if process goes false?
you will never get a message if process was successfull ;-)


  assertion_statement ::= [ label : ] assertion ;


  assertion ::=
  ASSERT condition
    [ REPORT expression ]
    [ SEVERITY expression ];





have a look to a shool example :

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-- hello_world.vhdl  Just output to the screen

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--                   This should be independent of whose VHDL you use

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--                   When using some vendors GUI, you have a learning curve

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--                   Using portable VHDL, it will run on all vendors

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--                   with implementations conforming to IEEE Std. 1076-1993

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entity hello_world is  -- test bench (top level like "main")

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end entity hello_world;

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library STD;                            -- you don't need STD, it is automatic

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library IEEE;                           -- but may need other libraries

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use IEEE.std_logic_1164.all;            -- basic logic types

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use STD.textio.all;                     -- basic I/O

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use IEEE.std_logic_textio.all;          -- I/O for logic types

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architecture test of hello_world is -- where declarations are placed

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  subtype word_32 is std_logic_vector(31 downto 0);  -- simple name

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  signal four_32 : word_32 := x"00000004";           -- just four in hex

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  signal counter : integer := 1;                     -- initialized counter

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begin  -- where parallel code is placed

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  my_print : process is                  -- a process is parallel

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               variable my_line : line;  -- type 'line' comes from textio

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             begin

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               write(my_line, string'("Hello World"));   -- formatting

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               writeline(output, my_line);               -- write to "output"

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               write(my_line, string'("four_32 = "));    -- formatting 

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               hwrite(my_line, four_32); -- format type std_logic_vector as hex

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               write(my_line, string'("  counter= "));

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               write(my_line, counter);  -- format 'counter' as integer

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               write(my_line, string'(" at time "));

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               write(my_line, now);                     -- format time

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               writeline(output, my_line);              -- write to display

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               wait;

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             end process my_print;

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end architecture test;

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-- compile/analyze this file, then simulate

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-- the output on the screen should contain the following lines (without "-- ")

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-- Hello World

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-- four_32 = 00000004  counter= 1 at time 0 NS


attached is a Vivado Hello World example

best wishes
rudi ;-)
Attached files:
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r_u_d_i Guest #4257111
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push#

perhabs you can have a look to a simply hello world, like this:

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use std.textio.all;

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entity hello_world is

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end hello_world;

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architecture behaviour of hello_world is

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begin

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process

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begin

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write (output, String'("Hello world!"));

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wait;

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end process;

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end behaviour;


;-)
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