I need to design an 4-bit comparator using hierarchical design. I have
the following code, which I think is right, but when i try to simulate
it in modelsim launch me an error saying error loading design.
VHDL N. wrote:> when i try to simulate it in modelsim launch me an error saying error> loading design.
How do you try to simulate it?
Did you start a new project and add those two code/files?
What (or where) is bitcompare?
I don't think its a good idea to use the name "bitcompare4" several
times (although it does not generate the problem here).
But for sure it isn't a good idea to use "bit" and "std_logic" as the
same (see the port in your entities port and the port of the component).
And also the port names MUST be the same in the entity port definition
and the components port.
After addig the missing bitcompare and having corrected the mistakes I
get some (little bit dubious) result with ISIM...