Hi
I need to design an 4-bit comparator using hierarchical design. I have
the following code, which I think is right, but when i try to simulate
it in modelsim launch me an error saying error loading design.
1 ---Design code---
2 library ieee ;
3 use ieee . std_logic_1164 . all ;
4 use ieee . std_logic_arith . all ;
5 use ieee . std_logic_unsigned . all ;
6
7 entity bitcompare4 is port
8 (
9 A , B : in bit_vector ( 3 downto 0 );
10 AgtB_o , AeqB_o , AltB_o : out bit
11 );
12 end bitcompare4 ;
13
14 architecture behave of bitcompare4 is
15 component bitcompare port
16 (
17 A , B , AgtB_i , AeqB_i : in bit ;
18 AgtB_o , AeqB_o : out bit
19 );
20 end component ;
21
22 signal AgtB_o1 , AeqB_o1 : bit_vector ( 3 downto 0 );
23 signal gnd , vcc : bit ;
24 begin
25
26 gnd <= '0' ;
27 vcc <= '1' ;
28 U1 : bitcompare port map
29 (
30 A => A ( 3 ),
31 B => B ( 3 ),
32 AgtB_i => gnd ,
33 AeqB_i => vcc ,
34 AgtB_o => AgtB_o1 ( 3 ),
35 AeqB_o => AeqB_o1 ( 3 )
36 );
37
38 U2 : bitcompare port map
39 (
40 A => A ( 2 ),
41 B => B ( 2 ),
42 AgtB_i => AgtB_o1 ( 3 ),
43 AeqB_i => AeqB_o1 ( 3 ),
44 AgtB_o => AgtB_o1 ( 2 ),
45 AeqB_o => AeqB_o1 ( 2 )
46 );
47
48 U3 : bitcompare port map
49 (
50 A => A ( 1 ),
51 B => B ( 1 ),
52 AgtB_i => AgtB_o1 ( 2 ),
53 AeqB_i => AeqB_o1 ( 2 ),
54 AgtB_o => AgtB_o1 ( 1 ),
55 AeqB_o => AeqB_o1 ( 1 )
56 );
57
58 U4 : bitcompare port map
59 (
60 A => A ( 0 ),
61 B => B ( 0 ),
62 AgtB_i => AgtB_o1 ( 1 ),
63 AeqB_i => AeqB_o1 ( 1 ),
64 AgtB_o => AgtB_o1 ( 0 ),
65 AeqB_o => AeqB_o1 ( 0 )
66 );
67 AgtB_o <= AgtB_o1 ( 0 );
68 AeqB_o <= AeqB_o1 ( 0 );
69 AltB_o <= not ( AgtB_o1 ( 0 ) or AeqB_o1 ( 0 ));
70
71 end behave ;
72
73 ---------------------------------------------------------------------------
74
75 ---TestBench---
76
77 library ieee ;
78 use ieee . std_logic_1164 . all ;
79
80 entity bitcompare4_tb is
81 end bitcompare4_tb ;
82
83 architecture bitcompare4 of bitcompare4_tb is
84
85 component bitcompare4 port
86 (
87 A , B : in std_logic_vector ( 3 downto 0 );
88 AgtB , AeqB , AltB : out std_logic
89 );
90 end component ;
91
92 signal A1 , B1 : std_logic_vector ( 3 downto 0 );
93 signal AgtB1 , AeqB1 , AltB1 : std_logic ;
94
95 begin
96
97 U1 : bitcompare4 port map
98 (
99 A => A1 ,
100 B => B1 ,
101 AgtB => AgtB1 ,
102 AeqB => AeqB1 ,
103 AltB => AltB1
104 );
105
106 A1 <= "0000" , "0010" after 20 ns , "1010" after 40 ns , "1011" after 60 ns ;
107 B1 <= "0000" , "0001" after 20 ns , "1010" after 40 ns , "1100" after 60 ns ;
108
109 end bitcompare4 ;
2015-09-29 08:35 :
Edited by Moderator
Did you see that a few lines above the edit box? 1 Reply
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VHDL N. wrote: > when i try to simulate it in modelsim launch me an error saying error
> loading design.
How do you try to simulate it?
Did you start a new project and add those two code/files?
What (or where) is bitcompare ?
I don't think its a good idea to use the name "bitcompare4" several
times (although it does not generate the problem here).
But for sure it isn't a good idea to use "bit" and "std_logic" as the
same (see the port in your entities port and the port of the component).
And also the port names MUST be the same in the entity port definition
and the components port.
After addig the missing bitcompare and having corrected the mistakes I
get some (little bit dubious) result with ISIM...
2015-09-29 08:58 :
Edited by Moderator
Thanks Lothar Miller, i found a solution to it already.
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