|
Posted on:
|
Hi I need to design an 4-bit comparator using hierarchical design. I have the following code, which I think is right, but when i try to simulate it in modelsim launch me an error saying error loading design.
---Design code--- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity bitcompare4 is port ( A,B : in bit_vector(3 downto 0); AgtB_o,AeqB_o,AltB_o : out bit ); end bitcompare4; architecture behave of bitcompare4 is component bitcompare port ( A,B,AgtB_i,AeqB_i : in bit; AgtB_o,AeqB_o : out bit ); end component; signal AgtB_o1,AeqB_o1 : bit_vector(3 downto 0); signal gnd, vcc : bit; begin gnd <= '0'; vcc <= '1'; U1 : bitcompare port map ( A => A(3), B => B(3), AgtB_i => gnd, AeqB_i => vcc, AgtB_o => AgtB_o1(3), AeqB_o => AeqB_o1(3) ); U2 : bitcompare port map ( A => A(2), B => B(2), AgtB_i => AgtB_o1(3), AeqB_i => AeqB_o1(3), AgtB_o => AgtB_o1(2), AeqB_o => AeqB_o1(2) ); U3 : bitcompare port map ( A => A(1), B => B(1), AgtB_i => AgtB_o1(2), AeqB_i => AeqB_o1(2), AgtB_o => AgtB_o1(1), AeqB_o => AeqB_o1(1) ); U4 : bitcompare port map ( A => A(0), B => B(0), AgtB_i => AgtB_o1(1), AeqB_i => AeqB_o1(1), AgtB_o => AgtB_o1(0), AeqB_o => AeqB_o1(0) ); AgtB_o <= AgtB_o1(0); AeqB_o <= AeqB_o1(0); AltB_o <= not ( AgtB_o1(0) or AeqB_o1(0)); end behave; --------------------------------------------------------------------------- ---TestBench--- library ieee; use ieee.std_logic_1164.all; entity bitcompare4_tb is end bitcompare4_tb; architecture bitcompare4 of bitcompare4_tb is component bitcompare4 port ( A,B : in std_logic_vector(3 downto 0); AgtB,AeqB,AltB : out std_logic ); end component; signal A1,B1 : std_logic_vector(3 downto 0); signal AgtB1,AeqB1,AltB1 : std_logic; begin U1 : bitcompare4 port map ( A => A1, B => B1, AgtB => AgtB1, AeqB => AeqB1, AltB => AltB1 ); A1 <= "0000", "0010" after 20 ns, "1010" after 40 ns, "1011" after 60 ns; B1 <= "0000", "0001" after 20 ns, "1010" after 40 ns, "1100" after 60 ns; end bitcompare4; |
:
Edited by Moderator
|
Posted on:
|
Attached files:
-
bitcompare.png
8.09 KB, 188 downloads
Did you see that a few lines above the edit box?
Reply Rules — please read before posting : Formatting options : [vhdl]VHDL code[/vhdl] |
VHDL N. wrote: > when i try to simulate it in modelsim launch me an error saying error > loading design. How do you try to simulate it? Did you start a new project and add those two code/files? What (or where) is bitcompare? I don't think its a good idea to use the name "bitcompare4" several times (although it does not generate the problem here). But for sure it isn't a good idea to use "bit" and "std_logic" as the same (see the port in your entities port and the port of the component). And also the port names MUST be the same in the entity port definition and the components port. After addig the missing bitcompare and having corrected the mistakes I get some (little bit dubious) result with ISIM...
:
Edited by Moderator
Watch this topic
Disable multi-page view