Lothar Miller wrote:
> Nayan Patel wrote:
>> but I get the following error message:
> You cannot synthesize a testbench on hardware. You can use a testbench
> only for simulation!
> Some hints:
> use ieee.numeric_std.all;
> use ieee.std_logic_unsigned.all;
> Using both of them together is not a good idea, because then you get
> some type definitions doubled...
> integer range SPI_2X_CLK_DIV-1 downto 0;
> A integer usually is defined with a ascending range...
> if spi_ssel_i = '1' then -- async
> NEVER EVER use an async input directly in a FSM. Let me repeat it once
> more: NEVER!!! If you don't sync in the external signel this will happen
> sooner or later, now or then:
> (its German, try Google translator)
I just figured out that the "spi_loopback.vhd" file is meant to be set
as the "Top-Level Entity".
I simulated the "spi_loopback.vhd" file but I get the following errors
as shown in the file attached. I am not sure why I am getting these