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Forum: FPGA, VHDL & Verilog [HELP] VHDL "cant infer register."


von Paulo Henrique Silva (Guest)


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The Quartus is detecting an error in my code, the error is this:

Error (10821): HDL error at state_machine.vhd(27): can't infer register 
for "atual" because its behavior does not match any supported register 
model

I do not know how to solve. I need to use "case" and "type" because my 
teacher asked.

I ask for help to solve. The code is below.
Thank you.
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--DECLARAÇÃO DE BIBLIOTECAS
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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--LIBRARY WORK;
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--USE work.digital_filter_package.all;
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--DECLARAÇÃO DA ENTIDADE
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ENTITY state_machine IS
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  PORT(
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    clk,d: IN STD_LOGIC
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  );
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END ENTITY state_machine;
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--DECLARAÇÃO DA ARQUITETURA DA ENTIDADE
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ARCHITECTURE behavioral OF state_machine IS
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  TYPE estado IS(amostrar,naoamostrar);
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  SIGNAL cancannot: STD_LOGIC;
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  SIGNAL atual: estado := naoamostrar;
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BEGIN
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  contandoeamostrando: PROCESS(clk,d,atual)
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    VARIABLE count: INTEGER := 0;
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  BEGIN
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    CASE atual IS
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      WHEN amostrar =>
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        cancannot <= '1';
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        IF(RISING_EDGE(clk)) THEN
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          count := 0;
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          atual <= naoamostrar;
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        END IF;
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      WHEN naoamostrar =>
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        cancannot <= '0';
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        IF(RISING_EDGE(clk)) THEN
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          IF(count<3333333) THEN
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            count := count + 1;
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          ELSE
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            atual <= amostrar;
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          END IF;
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        END IF;
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    END CASE;
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  END PROCESS;
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END ARCHITECTURE;

von Lothar M. (lkmiller) (Moderator)


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Paulo Henrique Silva wrote:
> can't infer register for "atual" because its behavior does not match any
> supported register model
The synthesizer cannot transfer your VHDL description to a hardware 
inside the FPGA.

And thats the problem:
IF(RISING_EDGE(clk)) THEN
Indeed not that line is the problem, but the place where it is located 
inside the code and also that this line is doubled inside the 
description. Where did you see this coding style? Nowhere? Its your 
idea?

If you want describe hardware in a synthesizeable manner you must do it 
in a way the synthesizer understands. And what the synthesizer 
understands is written in the synthesizers user guide. So have a close 
look for XST UG.

Try it a little more the "usual way". This here will be synthesizeable 
for sure, because its a straightforward synchronous design:
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  contandoeamostrando: PROCESS(clk)
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    VARIABLE count: INTEGER := 0;
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  BEGIN
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    IF(RISING_EDGE(clk)) THEN   -- a totally synchronous design
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      CASE atual IS
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        WHEN amostrar =>
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          cancannot <= '1';
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          count := 0;
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          atual <= naoamostrar;
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        WHEN naoamostrar =>
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          cancannot <= '0';
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          IF(count<3333333) THEN
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            count := count + 1;
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          ELSE
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            atual <= amostrar;
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          END IF;
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       END CASE;
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     END IF; 
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  END PROCESS;

: Edited by Moderator

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