Increasing dutycycle for an output signal

Robert Guest #4245985
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Hi all,

I want to increase the duty cycle slowly from 0%-50% in the period of 
0-10 ms for an output signal(150KHz) generated from a clock of 50MHz.

I am able to generate the output for 50%. I am not sure how to vary the 
duty cycle from 0-50% (between 0-10ms). Below is the code:

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entity Gen_150 is

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port ( sys_clk,reset: in std_logic; --sys_clk:50MHz

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a_out, b_out: out std_logic);       --a_out,b_out:150KHz

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end Gen_150 ;

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architecture bhv of Gen_150 is

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signal count: integer:=0;

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signal tmp : std_logic := '1';

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begin

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process(sys_clk,reset)

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begin

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if(reset='0') then

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count<=0;

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tmp<='1';

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elsif(sys_clk'event and sys_clk='1') then

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  count <=count+1;

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  if (count = 166) then   -- dutycycle=50% ((50000000/150000)/2)

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     tmp <= NOT tmp;

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     count<= 0;  

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  end if;

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end if;

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a_out <= tmp;

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b_out <= NOT tmp after 10ns; -- output delayed by 10ns

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end process;

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end bhv;


Thank you!
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Lothar M. Moderator (Company: Titel) #4246005
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Robert wrote:
> Below is the code:
> entity Gen_150 is
A VHDL code start well before the keyword "entity"...


> b_out <= NOT tmp after 10ns; -- output delayed by 10ns
Thats not synthesizeable! You know that?


> I want to increase the duty cycle slowly from 0%-50%
Try that and change the value of pwm:
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signal count: integer:=0;

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signal pwm: integer:=100;

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:

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:

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elsif(sys_clk'event and sys_clk='1') then

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  count <=count+1;

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  if (count = 332) then

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     count <= 0;  

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  end if;

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end if;

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tmp <= '1' when (count < pwm) else '0';

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:

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:

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end process;

Now you have a changing output signal. And the only thing you must du, 
is to produce a ramp on the "pwm" signal. Thats fairly easy...
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Robert Guest #4246097
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Thank you!
I implemented the ramping function with a counter=500000 (0-10ms). 
Please correct if I am wrong.

And I am getting an syntax error for the below:

tmp <= '1' when(count < pwm) else tmp <= '0';

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.numeric_std.ALL;

4
 

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entity Gen_150 is

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port ( sys_clk,reset: in std_logic;

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a_out, b_out: out std_logic);

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end Gen_150 ;

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architecture bhv of Gen_150 is

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signal count: integer:=0;

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signal tmp : std_logic := '1';

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signal counter: integer := 0;

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signal pwm: integer := 0;

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begin

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process(sys_clk,reset)

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begin

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if(reset='0') then

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count<=0;

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tmp<='1';

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elsif(sys_clk'event and sys_clk='1') then

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  count <=count+1;

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  --counter <= counter +1;

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  if (count = 332) then

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    -- tmp <= NOT tmp;

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     count<= 0;  

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  end if;

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end if;

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tmp <= '1' when(count < pwm) else tmp <= '0'; 

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a_out <= tmp;

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b_out <= NOT tmp;

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end process;

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Ramp : process (reset, sys_clk)

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begin

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  if reset = '0' then

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    pwm      <= 0;

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  elsif rising_edge(sys_clk)  then

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    counter <= counter +1;

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    if counter<=500000 then -- 500000 cycles =10ms

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        case  counter  is

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          when  50000     =>  pwm  <= 25;    

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          when  100000  =>  pwm  <= 33;  

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          when  150000  =>  pwm  <= 44;  

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          when  200000  =>  pwm  <= 66;  

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          when  250000  =>  pwm  <= 77;  

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          when  300000  =>  pwm  <= 99;            

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          when  350000  =>  pwm  <= 120;  

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          when  400000  =>  pwm  <= 132;  

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          when  450000  =>  pwm  <= 145;  

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          when  500000  =>  pwm  <= 166;  

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          when  others  =>  pwm  <= 0;    

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        end case;

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    else

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      pwm      <= 0;

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    end if;

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  end if;

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end process Ramp;

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end bhv;
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Lothar M. Moderator (Company: Titel) #4246111
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Robert wrote:
> And I am getting an syntax error for the below:
>
> tmp <= '1' when(count < pwm) else tmp <= '0';
Of course you do. What's the correct syntax for the when/else statement?
Why didn't you simply copy it from me?
Mine will not conclude in an error message.

And for the PWM value: let start it from 0. And then increment it every 
500000/166 clocks. So you will only need an additional counter from 0 to 
500000/166. And when the counter reaches that value you must reset it to 
0 and increment the PWM value until its 166.

You see that there's no whatsoever "case" statement necessary at all and 
the PWM value will increase smoothly from 0 to 166...
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Robert Guest #4246119
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Lothar M. wrote:
> Robert wrote:
>> And I am getting an syntax error for the below:
>>
>> tmp <= '1' when(count < pwm) else tmp <= '0';
> Of course you do. What's the correct syntax for the when/else statement?
> Why didn't you simply copy it from me?
> Mine will not conclude in an error message.

Sorry it was my mistake. Its fine now. But is the ramp function 
implemented correct?
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Robert Guest #4247830
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I want to add delays between the outputs (a_out and b_out).

Is it ok to add a min delay(is 10ns too much?) just by adding a temp 
register to delay out_b?

1
if(reset='0') then

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count<=0;

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tmp<='1';

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elsif(sys_clk'event and sys_clk='1') then

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:

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:

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end if;

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end if;

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a_out <= tmp; -- at falling edge

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d_b_out <= NOT tmp; -- at falling edge

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b_out <= d_b_out; -- delayed by 10ns - at rising edge

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:

13
:


I am not sure as the Input clock has a frequeny of 50MHz and the outputs 
are at 150KHz.
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Wil Guest #4266617
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How do I introduce a 180° phase shift between a_out and b_out. I tried 
using an inverting output. But when dutycycle is 10% for a_out, it is 
90% for b_out. But I want a 10% dutycycle for b_out with 180° phase 
shift.

Any suggestions?
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Lothar M. Moderator (Company: Titel) #4266707
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Wil wrote:
> How do I introduce a 180° phase shift between a_out and b_out.
> I tried using an inverting output.
A phase shift is only defined for sinusoidal signals. And then inverting 
is correct.

> How do I introduce a 180° phase shift between a_out and b_out.
What you want in fact is a delay of half the cycle duration for one of 
the signals.
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