Robert wrote:
> Below is the code:
> entity Gen_150 is
A VHDL code start well before the keyword "entity"...
> b_out <= NOT tmp after 10ns; -- output delayed by 10ns
Thats not synthesizeable! You know that?
> I want to increase the duty cycle slowly from 0%-50%
Try that and change the value of pwm:
1 | signal count: integer:=0;
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2 | signal pwm: integer:=100;
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3 | :
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4 | :
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5 | elsif(sys_clk'event and sys_clk='1') then
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6 | count <=count+1;
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7 |
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8 | if (count = 332) then
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9 | count <= 0;
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10 | end if;
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11 |
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12 | end if;
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13 |
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14 | tmp <= '1' when (count < pwm) else '0';
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15 | :
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16 | :
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17 | end process;
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Now you have a changing output signal. And the only thing you must du,
is to produce a ramp on the "pwm" signal. Thats fairly easy...