EmbDev.net

Forum: FPGA, VHDL & Verilog Carry Look Ahead Adder showing U at last bit position in SUM


von Rohan Narkhede (Guest)



Rate this post
useful
not useful
Hi,

I am getting U at the last bit position of SUM when I add two 32 bit 
numbers a and b by carry look ahead adder in VHDL.

my code is as follows:
1
library IEEE;
2
use IEEE.STD_LOGIC_1164.ALL;
3
4
entity cla_nbits is
5
generic (N : integer := 32);
6
    Port ( a : in STD_LOGIC_VECTOR (N-1 downto 0);
7
           b : in STD_LOGIC_VECTOR (N-1 downto 0);
8
           cin : in STD_LOGIC;
9
           sum : out STD_LOGIC_VECTOR (N-1 downto 0);
10
           cout : out STD_LOGIC);
11
end cla_nbits;
12
13
architecture Behavioral of cla_nbits is
14
15
signal g : STD_LOGIC_VECTOR (N-1 downto 0);
16
signal p : STD_LOGIC_VECTOR (N-1 downto 0);
17
signal c : STD_LOGIC_VECTOR (N-1 downto 0);
18
19
begin
20
21
g <= a and b;
22
p <= a xor b;
23
c(0) <= cin;
24
25
p1: process(p,g,c,cin)
26
begin
27
28
c(1) <= g(0) or (p(0) and cin);
29
for i in 1 to N-2 loop
30
    c(i+1) <= g(i) or (p(i) and c(i));
31
    end loop;
32
    
33
cout <= g(N-1) or (p(N-1) and c(N-1));
34
35
end process;
36
37
sum <= p xor c;
38
--sum(N-1 downto 0) <= p(N-1 downto 0) xor c(N-1 downto 0);
39
40
end Behavioral;

and the corresponding test bench i prepared is as follows:
1
library IEEE;
2
use IEEE.STD_LOGIC_1164.ALL;
3
4
entity tb_cla_nbit is
5
--  Port ( );
6
end tb_cla_nbit;
7
8
architecture tb of tb_cla_nbit is
9
10
component cla_nbits 
11
generic (N : integer := 32);
12
    Port ( a : in STD_LOGIC_VECTOR (N-1 downto 0);
13
           b : in STD_LOGIC_VECTOR (N-1 downto 0);
14
           cin : in STD_LOGIC;
15
           sum : out STD_LOGIC_VECTOR (N-1 downto 0);
16
           cout : out STD_LOGIC);
17
end component;
18
19
20
signal at, bt : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
21
signal cint : STD_LOGIC := '0';
22
signal sumt : STD_LOGIC_VECTOR (31 downto 0);
23
signal coutt : STD_LOGIC;
24
25
begin
26
27
uut1: cla_nbits port map (a=>at, b=>bt, cin=>cint, sum=>sumt, cout=>coutt);
28
29
p1: process
30
begin
31
at <= X"FFFFFFFF";
32
bt <= X"00000001";
33
wait for 50 ns;
34
35
at <= X"FFFFFFFF";
36
bt <= X"00000000";
37
cint <= '1';
38
wait for 50 ns;
39
40
at <= X"1A7E34B5";
41
bt <= X"11111111";
42
cint <= '1';
43
wait for 50 ns;
44
45
end process;
46
end tb;

Please let me know how to see the LSB bit in the SUM.

: Edited by Moderator
von Duke Scarring (Guest)


Attached files:

Rate this post
useful
not useful
You need to drive the signal from one process only:
1
library IEEE;
2
use IEEE.STD_LOGIC_1164.all;
3
4
entity cla_nbits is
5
    generic (N : integer := 32);
6
    port (a    : in  std_logic_vector (N-1 downto 0);
7
          b    : in  std_logic_vector (N-1 downto 0);
8
          cin  : in  std_logic;
9
          sum  : out std_logic_vector (N-1 downto 0);
10
          cout : out std_logic);
11
end cla_nbits;
12
13
architecture Behavioral of cla_nbits is
14
15
    signal g : std_logic_vector (N-1 downto 0);
16
    signal p : std_logic_vector (N-1 downto 0);
17
    signal c : std_logic_vector (N-1 downto 0);
18
19
begin
20
21
    g    <= a and b;
22
    p    <= a xor b;
23
24
    p1 : process(p, g, c, cin)
25
    begin
26
        c(0) <= cin;  -- not usable for the same signal outside the process
27
28
        c(1) <= g(0) or (p(0) and cin);
29
        for i in 1 to N-2 loop
30
            c(i+1) <= g(i) or (p(i) and c(i));
31
        end loop;
32
33
        cout <= g(N-1) or (p(N-1) and c(N-1));
34
35
    end process;
36
37
    sum <= p xor c;
38
--sum(N-1 downto 0) <= p(N-1 downto 0) xor c(N-1 downto 0);
39
40
end Behavioral;

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


Rate this post
useful
not useful
Rohan Narkhede wrote:
> my code is as follows:
> _____________________________________________________________________
Pls do not use that stylish line, but instead the [ vhdl ] tags as shown 
a few lines above each edit box:
1
Reply
2
Rules — please read before posting
3
   ....
4
Formatting options
5
    ....
6
    [vhdl]VHDL code[/vhdl]

von Rohan N. (Company: student) (rohan_n)


Rate this post
useful
not useful
Thank you so much Duke Scarring. This really works!

Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.