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Forum: FPGA, VHDL & Verilog Carry Look Ahead Adder showing U at last bit position in SUM


von Rohan Narkhede (Guest)


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Hi,

I am getting U at the last bit position of SUM when I add two 32 bit 
numbers a and b by carry look ahead adder in VHDL.

my code is as follows:
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity cla_nbits is
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generic (N : integer := 32);
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    Port ( a : in STD_LOGIC_VECTOR (N-1 downto 0);
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           b : in STD_LOGIC_VECTOR (N-1 downto 0);
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           cin : in STD_LOGIC;
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           sum : out STD_LOGIC_VECTOR (N-1 downto 0);
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           cout : out STD_LOGIC);
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end cla_nbits;
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architecture Behavioral of cla_nbits is
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signal g : STD_LOGIC_VECTOR (N-1 downto 0);
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signal p : STD_LOGIC_VECTOR (N-1 downto 0);
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signal c : STD_LOGIC_VECTOR (N-1 downto 0);
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begin
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g <= a and b;
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p <= a xor b;
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c(0) <= cin;
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p1: process(p,g,c,cin)
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begin
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c(1) <= g(0) or (p(0) and cin);
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for i in 1 to N-2 loop
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    c(i+1) <= g(i) or (p(i) and c(i));
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    end loop;
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cout <= g(N-1) or (p(N-1) and c(N-1));
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end process;
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sum <= p xor c;
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--sum(N-1 downto 0) <= p(N-1 downto 0) xor c(N-1 downto 0);
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end Behavioral;

and the corresponding test bench i prepared is as follows:
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity tb_cla_nbit is
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--  Port ( );
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end tb_cla_nbit;
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architecture tb of tb_cla_nbit is
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component cla_nbits 
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generic (N : integer := 32);
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    Port ( a : in STD_LOGIC_VECTOR (N-1 downto 0);
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           b : in STD_LOGIC_VECTOR (N-1 downto 0);
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           cin : in STD_LOGIC;
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           sum : out STD_LOGIC_VECTOR (N-1 downto 0);
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           cout : out STD_LOGIC);
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end component;
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signal at, bt : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
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signal cint : STD_LOGIC := '0';
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signal sumt : STD_LOGIC_VECTOR (31 downto 0);
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signal coutt : STD_LOGIC;
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begin
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uut1: cla_nbits port map (a=>at, b=>bt, cin=>cint, sum=>sumt, cout=>coutt);
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p1: process
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begin
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at <= X"FFFFFFFF";
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bt <= X"00000001";
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wait for 50 ns;
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at <= X"FFFFFFFF";
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bt <= X"00000000";
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cint <= '1';
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wait for 50 ns;
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at <= X"1A7E34B5";
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bt <= X"11111111";
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cint <= '1';
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wait for 50 ns;
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end process;
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end tb;

Please let me know how to see the LSB bit in the SUM.

: Edited by Moderator
von Duke Scarring (Guest)


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You need to drive the signal from one process only:
1
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity cla_nbits is
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    generic (N : integer := 32);
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    port (a    : in  std_logic_vector (N-1 downto 0);
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          b    : in  std_logic_vector (N-1 downto 0);
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          cin  : in  std_logic;
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          sum  : out std_logic_vector (N-1 downto 0);
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          cout : out std_logic);
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end cla_nbits;
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architecture Behavioral of cla_nbits is
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    signal g : std_logic_vector (N-1 downto 0);
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    signal p : std_logic_vector (N-1 downto 0);
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    signal c : std_logic_vector (N-1 downto 0);
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begin
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    g    <= a and b;
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    p    <= a xor b;
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    p1 : process(p, g, c, cin)
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    begin
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        c(0) <= cin;  -- not usable for the same signal outside the process
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        c(1) <= g(0) or (p(0) and cin);
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        for i in 1 to N-2 loop
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            c(i+1) <= g(i) or (p(i) and c(i));
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        end loop;
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        cout <= g(N-1) or (p(N-1) and c(N-1));
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    end process;
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    sum <= p xor c;
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--sum(N-1 downto 0) <= p(N-1 downto 0) xor c(N-1 downto 0);
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end Behavioral;

von Lothar M. (lkmiller) (Moderator)


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Rohan Narkhede wrote:
> my code is as follows:
> _____________________________________________________________________
Pls do not use that stylish line, but instead the [ vhdl ] tags as shown 
a few lines above each edit box:
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von Rohan N. (Company: student) (rohan_n)


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Thank you so much Duke Scarring. This really works!

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