how can is specify with generics how many ports i want and the width of each vector port?
For defining the number of ports and not only the width of each port, I would recommend using an array, which is defined within a package within the Package:
1 | type tIoArray is array (gNumber -1 downto 0) of std_logic_vector (gWidth - 1 downto 0); |
within the entity:
1 | entity myEnt is |
2 | port( |
3 | myInput : in tIoArray; |
4 | ...
|
5 | );
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