EmbDev.net

Forum: FPGA, VHDL & Verilog question to generics and ports


question to generics and ports
Author: Andreas F. (parafux)
Posted on:
Rate this post
0 ▲ useful
▼ not useful 
how can is specify with generics how many ports i want and the width of 
each vector port?

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: question to generics and ports
Author: Vipin L. (lal87)
Posted on:
Rate this post
0 ▲ useful
▼ not useful 
Look at this example,
http://vhdlguru.blogspot.in/2010/03/generics-in-vhdl-construction-of.html

Report post Edit Delete Quote selected text Reply Reply with quote
Re: question to generics and ports
Author: Fred (Guest)
Posted on:
Rate this post
0 ▲ useful
▼ not useful 
For defining the number of ports and not only the width of each port, I 
would recommend using an array, which is defined within a package

within the Package:
type tIoArray is array (gNumber -1 downto 0) of std_logic_vector (gWidth - 1 downto 0);

within the entity:
entity myEnt is
port(
  myInput : in tIoArray;
  ...
);

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.