question to generics and ports

For defining the number of ports and not only the width of each port, I 
would recommend using an array, which is defined within a package

within the Package:

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type tIoArray is array (gNumber -1 downto 0) of std_logic_vector (gWidth - 1 downto 0);

within the entity:

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entity myEnt is

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port(

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  myInput : in tIoArray;

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  ...

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);