how can is specify with generics how many ports i want and the width of each vector port?
Look at this example, http://vhdlguru.blogspot.in/2010/03/generics-in-vhdl-construction-of.html
For defining the number of ports and not only the width of each port, I would recommend using an array, which is defined within a package within the Package:
type tIoArray is array (gNumber -1 downto 0) of std_logic_vector (gWidth - 1 downto 0);
within the entity:
entity myEnt is port( myInput : in tIoArray; ... );