1 | Here I want to display "A" on my display using xc6lx9 tqg144 spartan 6 package..If I pass continuous '0' or '1' then its working very well But I f I am passing any particular pattern then it does not ...It will mix up data and randering in pixel....
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2 |
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3 | Code is given below :
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4 |
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5 | --------------------------------------------------------------------------------
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6 | --
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7 | -- FileName: vga_controller.vhd
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8 | -- Dependencies: none
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9 | -- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
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10 | --
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11 | -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
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12 | -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
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13 | -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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14 | -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
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15 | -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
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16 | -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
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17 | -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
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18 | -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
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19 | -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
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20 | --
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21 | -- Version History
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22 | -- Version 1.0 05/10/2013 Scott Larson
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23 | -- Initial Public Release
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24 | --
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25 | --------------------------------------------------------------------------------
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26 | LIBRARY ieee;
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27 | USE ieee.std_logic_1164.all;
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28 | USE ieee.numeric_std.all;
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29 | --USE ieee.std_logic_arith.all;
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30 | ENTITY vga_controller IS
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31 | GENERIC(
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32 | OFFSET : INTEGER := 1;
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33 | HEIGHT : INTEGER := 16;
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34 | WIDTH : INTEGER := 8;
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35 | START_X : INTEGER := 100;
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36 | START_Y : INTEGER := 80;
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37 | h_pulse : INTEGER := 120; --horiztonal sync pulse width in pixels
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38 | h_bp : INTEGER := 64; --horiztonal back porch width in pixels
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39 | h_pixels : INTEGER := 800; --horiztonal display width in pixels
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40 | h_fp : INTEGER := 56; --horiztonal front porch width in pixels
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41 | h_pol : STD_LOGIC := '1'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
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42 | v_pulse : INTEGER := 6; --vertical sync pulse width in rows
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43 | v_bp : INTEGER := 23; --vertical back porch width in rows
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44 | v_pixels : INTEGER := 600; --vertical display width in rows
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45 | v_fp : INTEGER := 37; --vertical front porch width in rows
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46 | v_pol : STD_LOGIC := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
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47 | PORT(
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48 | --cnt : inout std_logi
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49 | payal: inout std_logic_vector(1 downto 0):="10";
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50 | Y : inout std_logic:='0';
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51 | BELL : out std_logic;
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52 | clk25: in std_logic;
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53 | addr: inout std_logic_vector(10 downto 0);
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54 | data: inout std_logic_vector(7 downto 0):="00000000";
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55 | blue : out std_logic;
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56 | green : out std_logic;
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57 | red : out std_logic;
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58 | --clk25 : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
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59 | reset_n : IN STD_LOGIC; --active low asycnchronous reset
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60 | h_sync : INOUT STD_LOGIC; --horiztonal sync pulse
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61 | v_sync : OUT STD_LOGIC; --vertical sync pulse
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62 | disp_ena : INOUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
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63 | column : INOUT INTEGER; --horizontal pixel coordinate
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64 | row : INOUT INTEGER; --vertical pixel coordinate
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65 | n_blank : OUT STD_LOGIC; --direct blacking output to DAC
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66 | n_sync : OUT STD_LOGIC); --sync-on-green output to DAC
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67 | END vga_controller;
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68 | ARCHITECTURE behavior OF vga_controller IS
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69 | --signal clk25 : std_logic;
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70 | -- component clocking
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71 | -- port (
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72 | -- clk50 : in std_logic;
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73 | -- clk25 : out std_logic
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74 | -- );
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75 | -- end component;
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76 | --COMPONENT text
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77 | --PORT(
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78 | -- --cnt : out std_logic;
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79 | -- clk: in std_logic;
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80 | -- addr: inout std_logic_vector(10 downto 0);
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81 | -- data: out std_logic_vector(7 downto 0);
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82 | -- Y : inout std_logic
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83 | --
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84 | --);
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85 | --END COMPONENT;
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86 | CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
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87 | CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
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88 | |
89 | type rom_type is array (0 to 15)
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90 | of std_logic_vector(7 downto 0);
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91 | -- ROM definition
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92 | constant ROM: rom_type:=(
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93 | "00000000", -- 0
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94 | "00000000", -- 1
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95 | "00010000", -- 2 *
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96 | "00111000", -- 3 ***
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97 | "01101100", -- 4 ** **
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98 | "11000110", -- 5 ** **
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99 | "11000110", -- 6 ** **
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100 | "11111110", -- 7 *******
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101 | "11000110", -- 8 ** **
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102 | "11000110", -- 9 ** **
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103 | "11000110", -- a ** **
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104 | "11000110", -- b ** **
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105 | "00000000", -- c
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106 | "00000000", -- d
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107 | "00000000", -- e
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108 | "00000000" -- f
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109 | );
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110 | |
111 | BEGIN
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112 | -- CLKMGNT : clocking
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113 | -- port map (
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114 | -- clk50 => clk50,
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115 | -- clk25 => clk25
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116 | --
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117 | -- );
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118 | --generator : text
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119 | --port map(
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120 | --Y => Y,
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121 | --clk => pixel_clk,
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122 | --data => data,
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123 | --addr => addr
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124 | --);
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125 | BELL <= '1';
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126 | n_blank <= '1'; --no direct blanking
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127 | n_sync <= '0'; --no sync on green
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128 | -- pppp <= "11111111";
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129 | P1:PROCESS(clk25)
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130 | VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
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131 | VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
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132 | BEGIN
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133 | |
134 | -- IF(reset_n = '0') THEN --reset asserted
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135 | -- h_count := 0; --reset horizontal counter
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136 | -- v_count := 0; --reset vertical counter
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137 | -- h_sync <= NOT h_pol; --deassert horizontal sync
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138 | -- v_sync <= NOT v_pol; --deassert vertical sync
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139 | -- disp_ena <= '0'; --disable display
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140 | -- column <= 0; --reset column pixel coordinate
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141 | -- row <= 0; --reset row pixel coordinate
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142 | --
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143 | IF(clk25'EVENT AND clk25 = '1') THEN
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144 | --counters
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145 | |
146 | IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
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147 | h_count := h_count + 1;
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148 | ELSE
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149 | h_count := 0;
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150 | IF(v_count < v_period - 1) THEN --veritcal counter (rows)
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151 | v_count := v_count + 1;
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152 | ELSE
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153 | v_count := 0;
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154 | END IF;
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155 | END IF;
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156 | --horizontal sync signal
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157 | IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
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158 | h_sync <= NOT h_pol; --deassert horiztonal sync pulse
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159 | ELSE
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160 | h_sync <= h_pol; --assert horiztonal sync pulse
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161 | END IF;
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162 | --cnt <= h_sync;
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163 | --vertical sync signal
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164 | IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
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165 | v_sync <= NOT v_pol; --deassert vertical sync pulse
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166 | ELSE
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167 | v_sync <= v_pol; --assert vertical sync pulse
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168 | END IF;
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169 | |
170 | --set pixel coordinates
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171 | IF(h_count < h_pixels) THEN --horiztonal display time
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172 | column <= h_count; --set horiztonal pixel coordinate
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173 | END IF;
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174 | IF(v_count < v_pixels) THEN --vertical display time
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175 | row <= v_count; --set vertical pixel coordinate
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176 | END IF;
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177 | --set display enable output
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178 | IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
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179 | disp_ena <= '1'; --enable display
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180 | ELSE --blanking time
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181 | disp_ena <= '0'; --disable display
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182 | END IF;
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183 | END IF;
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184 | END PROCESS;
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185 | P2:PROCESS(disp_ena, row, column , h_sync)
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186 | VARIABLE I : INTEGER RANGE 0 TO 7 := 0;
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187 | VARIABLE CHARX : INTEGER RANGE 0 TO 7 := 0;
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188 | VARIABLE CHARY : INTEGER RANGE 0 TO 15 := 0;
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189 | BEGIN
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190 | IF(disp_ena = '1') THEN
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191 | if(column = START_X-1) then
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192 | if(row = START_Y)then
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193 | Y<= '1';
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194 | end if;
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195 | end if;
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196 | |
197 | if(row > (START_Y - OFFSET)and row < START_Y + HEIGHT) then
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198 | if(column > (START_X - OFFSET )and column < START_X + WIDTH) then
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199 | |
200 | |
201 | if(data(CHARX) = '0' or data(CHARX) = '1') then
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202 | IF (data(CHARX) = '0') THEN
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203 | red <='1';
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204 | green <= '1';
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205 | blue <= '1';
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206 | ELSE IF(data(CHARX) = '1') THEN
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207 | red <='0';
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208 | green <= '0';
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209 | blue <= '1';
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210 | END IF;
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211 | END IF;
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212 | if(CHARX = 7) then
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213 | CHARX := 0;
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214 | |
215 | if (CHARY = 15 ) then
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216 | CHARY := 0;
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217 | else
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218 | CHARY := CHARY+ 1;
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219 | Y<= '1';
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220 | end if;
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221 | |
222 | |
223 | else
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224 | CHARX :=CHARX + 1;
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225 | if (Y = '1') then
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226 | Y <= '0';
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227 | end if;
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228 | |
229 | -- IF(I = 7)THEN
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230 | -- I := 0;
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231 | -- Y<= '1';
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232 | -- ELSE
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233 | -- I := I+1;
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234 | -- if (Y = '1') then
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235 | -- Y <= '0';
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236 | -- end if;
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237 | -- END IF;
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238 | end if;
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239 | end if;
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240 | else
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241 | -- if (Y = '1') then
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242 | -- Y <= '0';
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243 | -- end if;
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244 | red <='1';
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245 | green <= '1';
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246 | blue <= '1';
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247 | end if;
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248 | else
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249 | red <='1';
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250 | green <= '1';
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251 | blue <= '1';
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252 | -- if (Y = '1') then
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253 | -- Y <= '0';
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254 | -- end if;
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255 | CHARX := 0;
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256 | end if;
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257 | ELSE
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258 | red <='0';
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259 | green <= '0';
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260 | blue <= '0';
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261 | END IF;
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262 | END PROCESS;
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263 | P3 : PROCESS (Y)
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264 | VARIABLE CNT : INTEGER RANGE 0 TO 15 := 0;
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265 | BEGIN
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266 | IF(Y = '1') THEN
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267 | data <= ROM(CNT);
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268 | IF (CNT = 15 )THEN
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269 | CNT := 0;
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270 | ELSE
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271 | CNT := CNT+1;
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272 | END IF;
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273 | |
274 | ELSE
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275 | data <= ROM(CNT);
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276 | END IF;
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277 | END PROCESS;
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278 | END behavior;
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