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Forum: FPGA, VHDL & Verilog VGA pins compatibility for Spartan 3 and Altera DE2 (verilog)


von Charan Mehta (Guest)


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There's a Verilog description written for Spartan 3, which is supposed 
to display something on a VGA. It has a 3-bit output "rgb" for the VGA 
(declared as output [2:0] rgb). In the pin assignments, there are 3 pins 
designated for the 3-bit rgb output.

If we want to write the Verilog description with the same functionality 
(displaying on the VGA) for an Altera DE2, do we have to change this VGA 
output for it to work properly? I'm confused because the standard pin 
assignments for the DE2 include 30 bits output for VGA. That is, there 
are 10 pins assigned each for VGA_R, VGA_G, and VGA_B.

So, how are we supposed to display the output on VGA of the Verilog 
description for Spartan 3 on an Altera DE2? What's the matter regarding 
the VGA pin assignments (3-bit vs. 30-bit) and how do we go about this 
compatibility issue?

von Duke Scarring (Guest)


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Charan Mehta wrote:
> What's the matter regarding
> the VGA pin assignments (3-bit vs. 30-bit)
It's the numer of selectable colors: 3 bit = 8 colors, 30 bit = 2^30 
colors.
You just need a mapping. The way from 8 to 2^30 is easy. Just copy the 
bit for the color (eg. red) in the vector of ten bits.

Duke

von Embe S. (Company: Sparrow SoftTech) (embesys)


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Helllo

1
Here I want to display "A" on my display using xc6lx9 tqg144 spartan 6 package..If I pass continuous '0' or '1' then its working very well But I f I am passing any particular pattern then it does not ...It will mix up data and randering in pixel....
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Code is given below :
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--------------------------------------------------------------------------------
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--
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-- FileName: vga_controller.vhd
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-- Dependencies: none
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-- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
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--
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-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
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-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
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-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
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-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
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-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
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-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
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-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
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--
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-- Version History
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-- Version 1.0 05/10/2013 Scott Larson
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-- Initial Public Release
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-- 
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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--USE ieee.std_logic_arith.all;
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ENTITY vga_controller IS
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GENERIC(
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OFFSET : INTEGER := 1;
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HEIGHT : INTEGER := 16;
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WIDTH : INTEGER := 8;
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START_X : INTEGER := 100;
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START_Y : INTEGER := 80;
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h_pulse : INTEGER := 120; --horiztonal sync pulse width in pixels
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h_bp : INTEGER := 64; --horiztonal back porch width in pixels
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h_pixels : INTEGER := 800; --horiztonal display width in pixels
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h_fp : INTEGER := 56; --horiztonal front porch width in pixels
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h_pol : STD_LOGIC := '1'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
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v_pulse : INTEGER := 6; --vertical sync pulse width in rows
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v_bp : INTEGER := 23; --vertical back porch width in rows
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v_pixels : INTEGER := 600; --vertical display width in rows
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v_fp : INTEGER := 37; --vertical front porch width in rows
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v_pol : STD_LOGIC := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
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PORT(
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--cnt : inout std_logi
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payal: inout std_logic_vector(1 downto 0):="10";
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Y : inout std_logic:='0';
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BELL : out std_logic;
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clk25: in std_logic;
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addr: inout std_logic_vector(10 downto 0);
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data: inout std_logic_vector(7 downto 0):="00000000";
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blue : out std_logic;
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green : out std_logic;
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red : out std_logic;
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--clk25 : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
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reset_n : IN STD_LOGIC; --active low asycnchronous reset
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h_sync : INOUT STD_LOGIC; --horiztonal sync pulse
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v_sync : OUT STD_LOGIC; --vertical sync pulse
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disp_ena : INOUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
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column : INOUT INTEGER; --horizontal pixel coordinate
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row : INOUT INTEGER; --vertical pixel coordinate
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n_blank : OUT STD_LOGIC; --direct blacking output to DAC
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n_sync : OUT STD_LOGIC); --sync-on-green output to DAC
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END vga_controller;
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ARCHITECTURE behavior OF vga_controller IS
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--signal clk25 : std_logic;
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-- component clocking
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-- port (
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-- clk50 : in std_logic;
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-- clk25 : out std_logic
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-- );
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-- end component;
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--COMPONENT text 
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--PORT(
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-- --cnt : out std_logic;
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-- clk: in std_logic;
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-- addr: inout std_logic_vector(10 downto 0);
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-- data: out std_logic_vector(7 downto 0);
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-- Y : inout std_logic
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--
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--);
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--END COMPONENT;
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CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
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CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
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type rom_type is array (0 to 15)
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of std_logic_vector(7 downto 0);
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-- ROM definition
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constant ROM: rom_type:=(
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"00000000", -- 0
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"00000000", -- 1
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"00010000", -- 2 *
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"00111000", -- 3 ***
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"01101100", -- 4 ** **
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"11000110", -- 5 ** **
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"11000110", -- 6 ** **
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"11111110", -- 7 *******
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"11000110", -- 8 ** **
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"11000110", -- 9 ** **
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"11000110", -- a ** **
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"11000110", -- b ** **
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"00000000", -- c
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"00000000", -- d
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"00000000", -- e
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"00000000" -- f
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); 
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BEGIN
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-- CLKMGNT : clocking
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-- port map (
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-- clk50 => clk50,
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-- clk25 => clk25
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-- 
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-- );
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--generator : text
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--port map(
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--Y => Y,
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--clk => pixel_clk,
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--data => data,
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--addr => addr
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--);
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BELL <= '1';
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n_blank <= '1'; --no direct blanking
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n_sync <= '0'; --no sync on green
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-- pppp <= "11111111";
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P1:PROCESS(clk25)
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VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
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VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
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BEGIN
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-- IF(reset_n = '0') THEN --reset asserted
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-- h_count := 0; --reset horizontal counter
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-- v_count := 0; --reset vertical counter
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-- h_sync <= NOT h_pol; --deassert horizontal sync
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-- v_sync <= NOT v_pol; --deassert vertical sync
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-- disp_ena <= '0'; --disable display
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-- column <= 0; --reset column pixel coordinate
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-- row <= 0; --reset row pixel coordinate
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-- 
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IF(clk25'EVENT AND clk25 = '1') THEN
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--counters
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IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
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h_count := h_count + 1;
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ELSE
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h_count := 0;
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IF(v_count < v_period - 1) THEN --veritcal counter (rows)
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v_count := v_count + 1;
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ELSE
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v_count := 0;
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END IF;
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END IF;
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--horizontal sync signal
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IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
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h_sync <= NOT h_pol; --deassert horiztonal sync pulse
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ELSE
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h_sync <= h_pol; --assert horiztonal sync pulse
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END IF;
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--cnt <= h_sync; 
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--vertical sync signal
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IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
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v_sync <= NOT v_pol; --deassert vertical sync pulse
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ELSE
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v_sync <= v_pol; --assert vertical sync pulse
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END IF;
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--set pixel coordinates
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IF(h_count < h_pixels) THEN --horiztonal display time
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column <= h_count; --set horiztonal pixel coordinate
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END IF;
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IF(v_count < v_pixels) THEN --vertical display time
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row <= v_count; --set vertical pixel coordinate
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END IF;
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--set display enable output
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IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
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disp_ena <= '1'; --enable display
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ELSE --blanking time
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disp_ena <= '0'; --disable display
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END IF;
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END IF;
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END PROCESS;
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P2:PROCESS(disp_ena, row, column , h_sync)
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VARIABLE I : INTEGER RANGE 0 TO 7 := 0;
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VARIABLE CHARX : INTEGER RANGE 0 TO 7 := 0;
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VARIABLE CHARY : INTEGER RANGE 0 TO 15 := 0;
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BEGIN
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IF(disp_ena = '1') THEN
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if(column = START_X-1) then
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if(row = START_Y)then
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Y<= '1';
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end if;
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end if;
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if(row > (START_Y - OFFSET)and row < START_Y + HEIGHT) then
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if(column > (START_X - OFFSET )and column < START_X + WIDTH) then
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if(data(CHARX) = '0' or data(CHARX) = '1') then
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IF (data(CHARX) = '0') THEN 
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red <='1';
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green <= '1';
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blue <= '1';
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ELSE IF(data(CHARX) = '1') THEN 
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red <='0';
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green <= '0';
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blue <= '1';
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END IF;
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END IF;
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if(CHARX = 7) then
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CHARX := 0;
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if (CHARY = 15 ) then
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CHARY := 0; 
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else
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CHARY := CHARY+ 1;
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Y<= '1';
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end if;
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else
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CHARX :=CHARX + 1;
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if (Y = '1') then
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Y <= '0'; 
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end if;
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-- IF(I = 7)THEN
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-- I := 0;
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-- Y<= '1';
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-- ELSE
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-- I := I+1;
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-- if (Y = '1') then
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-- Y <= '0';
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-- end if;
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-- END IF;
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end if;
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end if;
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else
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-- if (Y = '1') then
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-- Y <= '0';
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-- end if;
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red <='1';
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green <= '1';
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blue <= '1'; 
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end if;
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else
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red <='1';
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green <= '1';
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blue <= '1'; 
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-- if (Y = '1') then
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-- Y <= '0';
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-- end if; 
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CHARX := 0; 
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end if;
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ELSE
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red <='0';
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green <= '0';
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blue <= '0';
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END IF;
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END PROCESS;
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P3 : PROCESS (Y)
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VARIABLE CNT : INTEGER RANGE 0 TO 15 := 0;
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BEGIN
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IF(Y = '1') THEN
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data <= ROM(CNT); 
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IF (CNT = 15 )THEN
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CNT := 0;
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ELSE
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CNT := CNT+1;
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END IF;
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ELSE
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data <= ROM(CNT); 
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END IF;
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END PROCESS;
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END behavior;

von Embe S. (Company: Sparrow SoftTech) (embesys)


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jyhjgjnhgj

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