Here I want to display "A" on my display using xc6lx9 tqg144 spartan 6 package..If I pass continuous '0' or '1' then its working very well But I f I am passing any particular pattern then it does not ...It will mix up data and randering in pixel....
 
Code is given below :
 
--------------------------------------------------------------------------------
--
-- FileName: vga_controller.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 05/10/2013 Scott Larson
-- Initial Public Release
-- 
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--USE ieee.std_logic_arith.all;
ENTITY vga_controller IS
GENERIC(
OFFSET : INTEGER := 1;
HEIGHT : INTEGER := 16;
WIDTH : INTEGER := 8;
START_X : INTEGER := 100;
START_Y : INTEGER := 80;
h_pulse : INTEGER := 120; --horiztonal sync pulse width in pixels
h_bp : INTEGER := 64; --horiztonal back porch width in pixels
h_pixels : INTEGER := 800; --horiztonal display width in pixels
h_fp : INTEGER := 56; --horiztonal front porch width in pixels
h_pol : STD_LOGIC := '1'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : INTEGER := 6; --vertical sync pulse width in rows
v_bp : INTEGER := 23; --vertical back porch width in rows
v_pixels : INTEGER := 600; --vertical display width in rows
v_fp : INTEGER := 37; --vertical front porch width in rows
v_pol : STD_LOGIC := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
PORT(
--cnt : inout std_logi
payal: inout std_logic_vector(1 downto 0):="10";
Y : inout std_logic:='0';
BELL : out std_logic;
clk25: in std_logic;
addr: inout std_logic_vector(10 downto 0);
data: inout std_logic_vector(7 downto 0):="00000000";
blue : out std_logic;
green : out std_logic;
red : out std_logic;
--clk25 : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : INOUT STD_LOGIC; --horiztonal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : INOUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
column : INOUT INTEGER; --horizontal pixel coordinate
row : INOUT INTEGER; --vertical pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC); --sync-on-green output to DAC
END vga_controller;
ARCHITECTURE behavior OF vga_controller IS
--signal clk25 : std_logic;
-- component clocking
-- port (
-- clk50 : in std_logic;
-- clk25 : out std_logic
-- );
-- end component;
--COMPONENT text 
--PORT(
-- --cnt : out std_logic;
-- clk: in std_logic;
-- addr: inout std_logic_vector(10 downto 0);
-- data: out std_logic_vector(7 downto 0);
-- Y : inout std_logic
--
--);
--END COMPONENT;
CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column

type rom_type is array (0 to 15)
of std_logic_vector(7 downto 0);
-- ROM definition
constant ROM: rom_type:=(
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
); 

BEGIN
-- CLKMGNT : clocking
-- port map (
-- clk50 => clk50,
-- clk25 => clk25
-- 
-- );
--generator : text
--port map(
--Y => Y,
--clk => pixel_clk,
--data => data,
--addr => addr
--);
BELL <= '1';
n_blank <= '1'; --no direct blanking
n_sync <= '0'; --no sync on green
-- pppp <= "11111111";
P1:PROCESS(clk25)
VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
BEGIN

-- IF(reset_n = '0') THEN --reset asserted
-- h_count := 0; --reset horizontal counter
-- v_count := 0; --reset vertical counter
-- h_sync <= NOT h_pol; --deassert horizontal sync
-- v_sync <= NOT v_pol; --deassert vertical sync
-- disp_ena <= '0'; --disable display
-- column <= 0; --reset column pixel coordinate
-- row <= 0; --reset row pixel coordinate
-- 
IF(clk25'EVENT AND clk25 = '1') THEN
--counters

IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
h_count := h_count + 1;
ELSE
h_count := 0;
IF(v_count < v_period - 1) THEN --veritcal counter (rows)
v_count := v_count + 1;
ELSE
v_count := 0;
END IF;
END IF;
--horizontal sync signal
IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
h_sync <= NOT h_pol; --deassert horiztonal sync pulse
ELSE
h_sync <= h_pol; --assert horiztonal sync pulse
END IF;
--cnt <= h_sync; 
--vertical sync signal
IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
v_sync <= NOT v_pol; --deassert vertical sync pulse
ELSE
v_sync <= v_pol; --assert vertical sync pulse
END IF;

--set pixel coordinates
IF(h_count < h_pixels) THEN --horiztonal display time
column <= h_count; --set horiztonal pixel coordinate
END IF;
IF(v_count < v_pixels) THEN --vertical display time
row <= v_count; --set vertical pixel coordinate
END IF;
--set display enable output
IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
disp_ena <= '1'; --enable display
ELSE --blanking time
disp_ena <= '0'; --disable display
END IF;
END IF;
END PROCESS;
P2:PROCESS(disp_ena, row, column , h_sync)
VARIABLE I : INTEGER RANGE 0 TO 7 := 0;
VARIABLE CHARX : INTEGER RANGE 0 TO 7 := 0;
VARIABLE CHARY : INTEGER RANGE 0 TO 15 := 0;
BEGIN
IF(disp_ena = '1') THEN
if(column = START_X-1) then
if(row = START_Y)then
Y<= '1';
end if;
end if;

if(row > (START_Y - OFFSET)and row < START_Y + HEIGHT) then
if(column > (START_X - OFFSET )and column < START_X + WIDTH) then


if(data(CHARX) = '0' or data(CHARX) = '1') then
IF (data(CHARX) = '0') THEN 
red <='1';
green <= '1';
blue <= '1';
ELSE IF(data(CHARX) = '1') THEN 
red <='0';
green <= '0';
blue <= '1';
END IF;
END IF;
if(CHARX = 7) then
CHARX := 0;

if (CHARY = 15 ) then
CHARY := 0; 
else
CHARY := CHARY+ 1;
Y<= '1';
end if;


else
CHARX :=CHARX + 1;
if (Y = '1') then
Y <= '0'; 
end if;

-- IF(I = 7)THEN
-- I := 0;
-- Y<= '1';
-- ELSE
-- I := I+1;
-- if (Y = '1') then
-- Y <= '0';
-- end if;
-- END IF;
end if;
end if;
else
-- if (Y = '1') then
-- Y <= '0';
-- end if;
red <='1';
green <= '1';
blue <= '1'; 
end if;
else
red <='1';
green <= '1';
blue <= '1'; 
-- if (Y = '1') then
-- Y <= '0';
-- end if; 
CHARX := 0; 
end if;
ELSE
red <='0';
green <= '0';
blue <= '0';
END IF;
END PROCESS;
P3 : PROCESS (Y)
VARIABLE CNT : INTEGER RANGE 0 TO 15 := 0;
BEGIN
IF(Y = '1') THEN
data <= ROM(CNT); 
IF (CNT = 15 )THEN
CNT := 0;
ELSE
CNT := CNT+1;
END IF;

ELSE
data <= ROM(CNT); 
END IF;
END PROCESS;
END behavior;