Forum: FPGA, VHDL & Verilog boot NIOS and FPGA from EPCS flash

von jeorges F. (Company: xlue) (khal1985)

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Hi all,

I am having problems booting up my Nios C code from EPCS. I am building 
my own FPGA board, not using a demo board. I'm using Quartus 15.0 and 
DE0 NanoBoard( Cyclone IV as FPGA)
My application contains:

1. Clock Source
2. Nios II Processor
3. System ID
5. EPCS Serial Flash Controller
6. PIO
7. SDRAM Controller

I want to use SDRAM to store instructions and data for NIOS application. 
In the NIOS II Processor properties reset vector is set to base address 
of EPCS controller. Exceptions vector is set to base address to SDRAM. 
In the NIOS EDS for Eclipce I can debug my application, it works. Then, 
want to store the FPGA configuration data and the nios firmware in the 
EPCS following the steps below :

1) I generate the file.hex in NIOS terminal

2) Using Convert Programming Files in Quartus, I create a JIC file using 
the steps below:

2-a) Select EPCS64 (that is the flash chip i'm using)
2-b) Add SOF Page -> Page 0 -> Properties -> Address mode for selected 
pages: Set to START and Start Address = 0x0
2-c) Add file to SOF page: Add file.sof
2-d) Properties of file.sof select Compression
2-e) Add HEX data
2-f) Add File -> file.hex
2-g) Use absolute addressing offset( the offset was given in reset 
vector )

3) Generate JIC file -> NO issues.

4) Program EPCS device using Active Serial Programming. Add my JIC file. 
Programming succesful.

5) Power cycle my board. The hardware file starts, but the NIOS never 

So what is going wrong? I am programming using the USB Blaster. I am 
also not going through JTAG.

Any ideas?

Thanks in advance

Best regards

von Frank (Guest)

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You can give relative Adress with no Offset a try.
Also generate a MAP File to check if the Adresses are right (with no 
offset between sof and elf).

Another way is using the "Flash Programmer Tool" in the NIOS Toolchain 
(Eclipse). Thats a little helper Tool to generate flash Files and 
Download to the EPCS.

von Frank (Guest)

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After Programming and a Power OFF/ON cycle you can check the results 
jtagconfig -n

von jeorges F. (Company: xlue) (khal1985)

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Hi Frank,

Thank you for your answer. I finally success to boot both hardware and 
software from flash, the problem was i think the clock, because it was 
configured to be 100 Mhz for the flash controller. When i modified it, 
to be 25 Mhz, it's ok.

But, now i'm facing another problem. When i try to run the NIOS over 
JTAG, i can't see any modification. It seems to be kind of jtag 
communication problem. In the Nios console, i can't see the "hello word" 
It worked for me before, it's strange.

with the jtagconfig -n command, i get this message (the picture joined)

Best regards

von jeorges F. (Company: xlue) (khal1985)

Attached files:

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the picture more bigger

von David Koppel (Guest)

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Has anyone tried to run more than one NIOS out of EPCS? I've got four 
NIOS's defined in the .sof and I program them in one after the other. 
Only the last one works. I suspect it's because I have to give them all 
the same offset so they overwrite each other. Any ideas?


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