When I compmile my project in Quartus (15.0 Webedition) I get following error message: Can't compile duplicate declarations of entity "xyz" into library "test" When I click on the error message it opens the file "xyz.v". What I see is the Verilog-file although the project only uses vhdl-files! There is allready a file with the name "xyz.vhd" in the project. Under Settings -> Files there are only vhdl-files included. Now I am wondering why the compiler still sees a Verilog-File. Thanks in advance!
Hugo H. wrote: > Now I am wondering why the compiler still sees a Verilog-File. Do you have some kind of precompiled core in your system (e.g. a divider or a multiplier or somewhat else)?
No. I am using a Nios and two other blocks (QSYS) like an SPI interface and some I/O - that's all. What I changed in the meantime is the IP Settings -> IP generation HDL preference to VHDL. Now I get following error message: 10430 VHDL Primary Unit Declatation erro at xyz.vhd: primary unit "XYZ" already exists in library "xyz". A click of this file opens (again) the xyz.vhd (not Verilog file!). But in my project I have the file "XYZ.vhd" (capitol letters). Therefore it is quite the same problem again. Why quartus generates such file in the database which is almost the same as my file in the project folder which has a reference in other files?